The ZL30683 offers three DPLL channels of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, these devices offer new and improved features for 5G transport and wireless infrastructure equipment. Each device integrates all features required by line card PLL. High integration along with ultra-low jitter make these devices ideal for use in frequency translation from backplane clock to frequencies required by PHY devices, jitter filtering, and holdover in case both active and redundant timing cards fail.
Click here for secure documentation
Additional Features
Key Features
Three independent DPLL channels
Precise phase/frequency measurement and tuning lower system latency to meet 4G LTE, 5G & Wireless Infrastructure
Precise chip-to-chip time interfaces use less backplane traces for 1PPS distribution for chassis systems
Split oscillator option lowers cost, lowers jitter, and provides redundancy
Excellent jitter performance of <300 fs RMS in the 12 kHz to 20 MHz band meets jitter requirements for 10G/40G and 100G PHYs
Two programmable ultra-low jitter synthesizers generate any frequency from 0.5 Hz to 1045 MHz
One programmable general purpose synthesizer generates any clock from 0.5 Hz to 180 MHz
8 differential or 16 single ended ultra-low jitter outputs plus two general purpose CMOS outputs
Programmable output advancement/delay to accommodate trace delays or compensate for system routing paths
Up to three programmable digital PLLs/NCOs with loop bandwidth from 14 Hz to 470 Hz synchronize to any clock rate from 0.5 Hz to 900 MHz
Accepts up to 10 differential or 10 single ended input references
Full reference monitoring of electrical failures
Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 0.1 ppb
Any input reference can be fed with clock, sync (frame pulse), clock /sync pair or clock modulated with sync pulse (embedded PPS ePPS and embedded PP2S ePP2S)
Easy Configuration and dynamic programming via SPI/I2C interface
Factory programming available
Operates from a single crystal resonator or clock oscillator
The ZL30683 offers three DPLL channels of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, these devices offer new and improved features for 5G transport and wireless infrastructure equipment. Each device integrates all features required by line card PLL. High integration along with ultra-low jitter make these devices ideal for use in frequency translation from backplane clock to frequencies required by PHY devices, jitter filtering, and holdover in case both active and redundant timing cards fail.
Click here for secure documentation
Additional Features
- Key Features
- Three independent DPLL channels
- Precise phase/frequency measurement and tuning lower system latency to meet 4G LTE, 5G & Wireless Infrastructure
- Precise chip-to-chip time interfaces use less backplane traces for 1PPS distribution for chassis systems
- Split oscillator option lowers cost, lowers jitter, and provides redundancy
- Excellent jitter performance of <300 fs RMS in the 12 kHz to 20 MHz band meets jitter requirements for 10G/40G and 100G PHYs
- Two programmable ultra-low jitter synthesizers generate any frequency from 0.5 Hz to 1045 MHz
- One programmable general purpose synthesizer generates any clock from 0.5 Hz to 180 MHz
- 8 differential or 16 single ended ultra-low jitter outputs plus two general purpose CMOS outputs
- Programmable output advancement/delay to accommodate trace delays or compensate for system routing paths
- Up to three programmable digital PLLs/NCOs with loop bandwidth from 14 Hz to 470 Hz synchronize to any clock rate from 0.5 Hz to 900 MHz
- Accepts up to 10 differential or 10 single ended input references
- Full reference monitoring of electrical failures
- Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 0.1 ppb
- Any input reference can be fed with clock, sync (frame pulse), clock /sync pair or clock modulated with sync pulse (embedded PPS ePPS and embedded PP2S ePP2S)
- Easy Configuration and dynamic programming via SPI/I2C interface
- Factory programming available
- Operates from a single crystal resonator or clock oscillator
