The ZL30143 System Synchronizer and SETS device is a highly integrated device that provides all of the functionality that is required for a central timing card in carrier grade network equipment. The basic functions of a central timing card include: • Input reference monitoring for both frequency accuracy and phase irregularities • Automatic input reference selection • Support of both external timing and line timing modes • Hitless reference switching • Wander and jitter filtering • Master/slave crossover for minimizing phase alignment between redundant timing cards • Independent derived output timing path for support of the SETS functionality
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Additional Features
Typical Applications
ITU-T G.8262 System Timing Cards which support 1 GbE and 10 GbE interfaces
Telcordia GR-253 Carrier Grade SONET/SDH Stratum 3 System Timing Cards
System Timing Cards which supports ITU-T G.781 SETS (SDH Equipment Timing Source)
Features & Benefits
Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks (EEC option 1 and 2)
Supports the requirements of Telcordia GR-1244 Stratum 3 and GR-253, ITU-T G.813, and G.781 SETS
Supports ITU-T G.823, G.824 and G.8261 for 2048 kbit/s and 1544 kbit/s interfaces
Meets the SONET/SDH jitter generation requirements up to OC-48/STM-16
Synchronizes to telecom reference clocks (2 kHz, N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz)
Supports composite clock inputs (64 kHz, 64 kHz + 8 kHz, 64kHz + 8 kHz + 400 Hz)
Generates standard SONET/SDH clock rates (e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 622.08 MHz) or Ethernet clock rates (e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for synchronizing Gigabit Ethernet PHYs
Programmable output synthesizers (P0, P1) generate telecom clock frequencies from any multiple of 8 kHz up to 100 MHz
Generates several styles of telecom frame pulses with selectable pulse width, polarity and frequency
Provides two DPLLs which are independently configurable through a serial interface
Internal state machine automatically controls mode of operation (free-run, locked, holdover)
Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities
Provides automatic reference switching and holdover during loss of reference input
Supports master/slave configuration and dynamic input to output delay compensation for AdvancedTCA?
Configurable input to output delay and output to output phase alignment
The ZL30143 System Synchronizer and SETS device is a highly integrated device that provides all of the
functionality that is required for a central timing card in carrier grade network equipment. The basic functions of a
central timing card include:
• Input reference monitoring for both frequency accuracy and phase irregularities
• Automatic input reference selection
• Support of both external timing and line timing modes
• Hitless reference switching
• Wander and jitter filtering
• Master/slave crossover for minimizing phase alignment between redundant timing cards
• Independent derived output timing path for support of the SETS functionality
Click here for secure documentation
Additional Features
- Typical Applications
- ITU-T G.8262 System Timing Cards which support 1 GbE and 10 GbE interfaces
- Telcordia GR-253 Carrier Grade SONET/SDH Stratum 3 System Timing Cards
- System Timing Cards which supports ITU-T G.781 SETS (SDH Equipment Timing Source)
- Features & Benefits
- Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks (EEC option 1 and 2)
- Supports the requirements of Telcordia GR-1244 Stratum 3 and GR-253, ITU-T G.813, and G.781 SETS
- Supports ITU-T G.823, G.824 and G.8261 for 2048 kbit/s and 1544 kbit/s interfaces
- Meets the SONET/SDH jitter generation requirements up to OC-48/STM-16
- Synchronizes to telecom reference clocks (2 kHz, N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz)
- Supports composite clock inputs (64 kHz, 64 kHz + 8 kHz, 64kHz + 8 kHz + 400 Hz)
- Generates standard SONET/SDH clock rates (e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 622.08 MHz) or Ethernet clock rates (e.g., 25 MHz, 50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for synchronizing Gigabit Ethernet PHYs
- Programmable output synthesizers (P0, P1) generate telecom clock frequencies from any multiple of 8 kHz up to 100 MHz
- Generates several styles of telecom frame pulses with selectable pulse width, polarity and frequency
- Provides two DPLLs which are independently configurable through a serial interface
- Internal state machine automatically controls mode of operation (free-run, locked, holdover)
- Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities
- Provides automatic reference switching and holdover during loss of reference input
- Supports master/slave configuration and dynamic input to output delay compensation for AdvancedTCA?
- Configurable input to output delay and output to output phase alignment
