Microchip Technology, Inc. SY898533L

Description
The SY898533L is a 3.3V, low skew, 1:4 LVPECL fanout buffer with two selectable clock input pairs. Most standard differential input levels can be applied to the CLK, /CLK pair while LVPECL, CML, or SSTL input levels can be applied to the PCLK, /PCLK pair. To eliminate runt pulses on the outputs during asynchronous assertion/de-asserti on of the clock enable pin, the clock enable is synchronized with the input signal.The SY898533L operates from a 3.3V ±5% supply and is guaranteed over the full industrial temperature range of 0°C to +70°C. The SY898533L is part of Micrel's highspeed, Precision Edge® product line. Additional Features Provides four differential 3.3V LVPECL copies Selects between differential CLK, /CLK or LVPECL clock inputs CLK, /CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL input levels PCLK, /PCLK pair accepts LVPECL, CML, SSTL input levels 650MHz Maximum output frequency <1.4ns Propagation delay (In-to-Q) <30ps Output skew <150ps Part-to-part skew 3.3V ±5% supply voltage 0°C to +70°C temperature operating range Available in a 20-pin TSSOP package
Datasheet
Description
The SY898533L is a 3.3V, low skew, 1:4 LVPECL fanout buffer with two selectable clock input pairs. Most standard differential input levels can be applied to the CLK, /CLK pair while LVPECL, CML, or SSTL input levels can be applied to the PCLK, /PCLK pair. To eliminate runt pulses on the outputs during asynchronous assertion/de-asserti on of the clock enable pin, the clock enable is synchronized with the input signal.The SY898533L operates from a 3.3V ±5% supply and is guaranteed over the full industrial temperature range of 0°C to +70°C. The SY898533L is part of Micrel's highspeed, Precision Edge® product line. Additional Features Provides four differential 3.3V LVPECL copies Selects between differential CLK, /CLK or LVPECL clock inputs CLK, /CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL input levels PCLK, /PCLK pair accepts LVPECL, CML, SSTL input levels 650MHz Maximum output frequency <1.4ns Propagation delay (In-to-Q) <30ps Output skew <150ps Part-to-part skew 3.3V ±5% supply voltage 0°C to +70°C temperature operating range Available in a 20-pin TSSOP package
Datasheet

Suppliers

Company
Product
Description
Supplier Links
 - SY898533L - Microchip Technology, Inc.
Chandler, AZ, United States
The SY898533L is a 3.3V, low skew, 1:4 LVPECL fanout buffer with two selectable clock input pairs. Most standard differential input levels can be applied to the CLK, /CLK pair while LVPECL, CML, or SSTL input levels can be applied to the PCLK, /PCLK pair. To eliminate runt pulses on the outputs during asynchronous assertion/de-asserti on of the clock enable pin, the clock enable is synchronized with the input signal.The SY898533L operates from a 3.3V ±5% supply and is guaranteed over the full industrial temperature range of 0°C to +70°C. The SY898533L is part of Micrel's highspeed, Precision Edge® product line. Additional Features Provides four differential 3.3V LVPECL copies Selects between differential CLK, /CLK or LVPECL clock inputs CLK, /CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL input levels PCLK, /PCLK pair accepts LVPECL, CML, SSTL input levels 650MHz Maximum output frequency <1.4ns Propagation delay (In-to-Q) <30ps Output skew <150ps Part-to-part skew 3.3V ±5% supply voltage 0°C to +70°C temperature operating range Available in a 20-pin TSSOP package

The SY898533L is a 3.3V, low skew, 1:4 LVPECL fanout buffer with two selectable clock input pairs. Most standard differential input levels can be applied to the CLK, /CLK pair while LVPECL, CML, or SSTL input levels can be applied to the PCLK, /PCLK pair. To eliminate runt pulses on the outputs during asynchronous assertion/de-assertion of the clock enable pin, the clock enable is synchronized with the input signal.The SY898533L operates from a 3.3V ±5% supply and is guaranteed over the full industrial temperature range of 0°C to +70°C. The SY898533L is part of Micrel's highspeed, Precision Edge® product line.

Additional Features

  • Provides four differential 3.3V LVPECL copies
  • Selects between differential CLK, /CLK or LVPECL clock inputs
  • CLK, /CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL input levels
  • PCLK, /PCLK pair accepts LVPECL, CML, SSTL input levels
  • 650MHz Maximum output frequency
  • <1.4ns Propagation delay (In-to-Q)
  • <30ps Output skew
  • <150ps Part-to-part skew
  • 3.3V ±5% supply voltage
  • 0°C to +70°C temperature operating range
  • Available in a 20-pin TSSOP package
Supplier's Site Datasheet

Technical Specifications

  Microchip Technology, Inc.
Product Category Amplifier and Comparator Chips
Product Number SY898533L
Package Type ['TSSOP']
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