The SY89830U is a high-speed, 2.5GHz differential PECL 1:4 fanout buffer optimized for ultra-low skew applications. Within device skew is guaranteed to be less than 25ps over temperature and supply voltage. The wide supply voltage operation allows this fanout buffer to operate in 2.5V, 3.3V, and 5V systems.The SY89830U features a 2:1 input MUX, making it an ideal solution for redundant clock switchover applications. If only one input pair is used, the other pair may be left floating. In addition, this device includes a synchronous enable pin that forces the outputs into a fixed logic state. Enable or disable state is initiated only after the outputs are in a LOW state, thus eliminating the possibility of a "runt" clock pulse.The SY89830U I/O are fully differential and 100K ECL compatible. Differential 10K ECL logic can interface directly into the SY89830U inputs.The SY89830U is part of Micrel's high-speed precision edge timing and distribution family. For applications that require a different I/O combination, choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock generators.
Additional Features
Guaranteed AC parameters over temp/voltage:
>2.5GHz fMAX
<25ps within-device skew
<225ps tr/tf time
<450ps prop delay
Low jitter design:
<1psRMS cycle-to-cycle jitter
<15psPP total jitter
2:1 Differential MUX input
Flexible supply voltage: 2.5V/3.3V/5V
Wide operating temperature range: -40°C to +85°C
100K ECL compatible outputs
Inputs accept PECL/LVPECL/ECL/HSTL logic levels
Available in a 16-pin TSSOP package
The SY89830U is a high-speed, 2.5GHz differential PECL 1:4 fanout buffer optimized for ultra-low skew applications. Within device skew is guaranteed to be less than 25ps over temperature and supply voltage. The wide supply voltage operation allows this fanout buffer to operate in 2.5V, 3.3V, and 5V systems.The SY89830U features a 2:1 input MUX, making it an ideal solution for redundant clock switchover applications.
If only one input pair is used, the other pair may be left floating. In addition, this device includes a synchronous enable pin that forces the outputs into a fixed logic state. Enable or disable state is initiated only after the outputs are in a LOW state, thus eliminating the possibility of a "runt" clock pulse.The SY89830U I/O are fully differential and 100K ECL compatible. Differential 10K ECL logic can interface directly into the SY89830U inputs.The SY89830U is part of Micrel's high-speed precision edge timing and distribution family. For applications that require a different I/O combination, choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock generators.
Additional Features
- Guaranteed AC parameters over temp/voltage:
- >2.5GHz fMAX
- <25ps within-device skew
- <225ps tr/tf time
- <450ps prop delay
- Low jitter design:
- <1psRMS cycle-to-cycle jitter
- <15psPP total jitter
- 2:1 Differential MUX input
- Flexible supply voltage: 2.5V/3.3V/5V
- Wide operating temperature range: -40°C to +85°C
- 100K ECL compatible outputs
- Inputs accept PECL/LVPECL/ECL/HSTL logic levels
- Available in a 16-pin TSSOP package
