The SY89829U is a High Performance dual 1:10 or single 1:20 LVPECL Clock Driver. The part is designed for use in low voltage (2.5V/3.3V) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed from either LVDS or LVPECL by the CLK_SEL pin. The LVDS inputs include a 100Ω internal termination across the input pair, thus eliminating any need for external termination. The 2:1 input mux makes this device an ideal choice for redundant clock applications that need to switch between two reference clocks. The output enable (OE) is synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89829U features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.)--performance previously unachievable in a standard product having such a high number of outputs. The SY89829U is available in a single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew.
Additional Features
Dual 1:10 fanout buffer/translator
Accepts LVPECL or LVDS inputs
Multiplexed inputs ideal for redundant clock switchover
Guaranteed AC parameters:
>2GHz fMAX (toggle)
<50ps ch-ch skew
LVDS input includes 100Ω internal termination
Low supply voltage: 2.5V, 3.3V
-40°C to +85°C temperature range
Output enable (OE) pin
Available in 64 EPAD-TQFP
The SY89829U is a High Performance dual 1:10 or single 1:20 LVPECL Clock Driver. The part is designed for use in low voltage (2.5V/3.3V) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed from either LVDS or LVPECL by the CLK_SEL pin. The LVDS inputs include a 100Ω internal termination across the input pair, thus eliminating any need for external termination. The 2:1 input mux makes this device an ideal choice for redundant clock applications that need to switch between two reference clocks.
The output enable (OE) is synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89829U features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.)--performance previously unachievable in a standard product having such a high number of outputs. The SY89829U is available in a single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew.
Additional Features
- Dual 1:10 fanout buffer/translator
- Accepts LVPECL or LVDS inputs
- Multiplexed inputs ideal for redundant clock switchover
- Guaranteed AC parameters:
- >2GHz fMAX (toggle)
- <50ps ch-ch skew
- LVDS input includes 100Ω internal termination
- Low supply voltage: 2.5V, 3.3V
- -40°C to +85°C temperature range
- Output enable (OE) pin
- Available in 64 EPAD-TQFP
