Microchip Technology, Inc. SY89828L

Description
The SY89828L is a precision fanout buffer with 20 differential LVDS (Low Voltage Differential Swing) output pairs. The part is designed for use in low voltage 3.3V applications that require a large number of outputs to drive precisely aligned, ultra low-skew signals to their destination.The input is multiplexed from either LVDS or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK_SEL1 and CLK_SEL2 pins. The Output Enables (OE1 and OE2) are synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89828L features a low pin-to-pin skew of less than 50ps--performance previously unachievable in a standard product having such a high number of outputs.The SY89828L is available in a single space saving package, enabling a lower overall cost solution. Additional Features High-performance dual 1:10, 1GHz LVDS fanout buffer/translator Two banks of 10 differential LVDS outputs Guaranteed AC parameters over temperature and voltage: >1GHz fMAX <50ps within device skew <400ps tr/tf time Each bank includes a 2:1 input mux 2:1 mux input accepts LVDS and LVPECL Low jitter performance <1psRMS cycle-to-cycle jitter <1psPP total jitter 3.3V supply voltage Output enable function LVDS input includes internal 100Ω termination Available in a 64-Pin EPAD-TQFP
Description
The SY89828L is a precision fanout buffer with 20 differential LVDS (Low Voltage Differential Swing) output pairs. The part is designed for use in low voltage 3.3V applications that require a large number of outputs to drive precisely aligned, ultra low-skew signals to their destination.The input is multiplexed from either LVDS or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK_SEL1 and CLK_SEL2 pins. The Output Enables (OE1 and OE2) are synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89828L features a low pin-to-pin skew of less than 50ps--performance previously unachievable in a standard product having such a high number of outputs.The SY89828L is available in a single space saving package, enabling a lower overall cost solution. Additional Features High-performance dual 1:10, 1GHz LVDS fanout buffer/translator Two banks of 10 differential LVDS outputs Guaranteed AC parameters over temperature and voltage: >1GHz fMAX <50ps within device skew <400ps tr/tf time Each bank includes a 2:1 input mux 2:1 mux input accepts LVDS and LVPECL Low jitter performance <1psRMS cycle-to-cycle jitter <1psPP total jitter 3.3V supply voltage Output enable function LVDS input includes internal 100Ω termination Available in a 64-Pin EPAD-TQFP
Datasheet
Datasheet Summary
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The SY89828L is a high-performance dual 1:10 fanout buffer designed for 3.3V applications, featuring 20 differential LVDS output pairs. It supports input multiplexing from both LVDS and LVPECL sources, allowing for flexible integration in various systems. The device guarantees a maximum frequency of over 1GHz and maintains a low pin-to-pin skew of less than 50ps, ensuring precise signal alignment. Additionally, it offers low jitter performance with less than 1ps RMS cycle-to-cycle jitter and less than 1ps peak-to-peak total jitter. The SY89828L includes synchronous output enable functions to prevent runt clock pulses during transitions and features internal termination for LVDS inputs. It is packaged in a 64-Pin EPAD-TQFP, making it suitable for space-constrained designs. This product is ideal for applications in enterprise networking, high-end servers, and communications systems.

Datasheet Summary
Powered by GS/AI

The SY89828L is a high-performance dual 1:10 fanout buffer designed for 3.3V applications, featuring 20 differential LVDS output pairs. It supports input multiplexing from both LVDS and LVPECL sources, allowing for flexible integration in various systems. The device guarantees a maximum frequency of over 1GHz and maintains a low pin-to-pin skew of less than 50ps, ensuring precise signal alignment. Additionally, it offers low jitter performance with less than 1ps RMS cycle-to-cycle jitter and less than 1ps peak-to-peak total jitter. The SY89828L includes synchronous output enable functions to prevent runt clock pulses during transitions and features internal termination for LVDS inputs. It is packaged in a 64-Pin EPAD-TQFP, making it suitable for space-constrained designs. This product is ideal for applications in enterprise networking, high-end servers, and communications systems.

Suppliers

Company
Product
Description
Supplier Links
 - SY89828L - Microchip Technology, Inc.
Chandler, AZ, United States
The SY89828L is a precision fanout buffer with 20 differential LVDS (Low Voltage Differential Swing) output pairs. The part is designed for use in low voltage 3.3V applications that require a large number of outputs to drive precisely aligned, ultra low-skew signals to their destination.The input is multiplexed from either LVDS or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK_SEL1 and CLK_SEL2 pins. The Output Enables (OE1 and OE2) are synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89828L features a low pin-to-pin skew of less than 50ps--performance previously unachievable in a standard product having such a high number of outputs.The SY89828L is available in a single space saving package, enabling a lower overall cost solution. Additional Features High-performance dual 1:10, 1GHz LVDS fanout buffer/translator Two banks of 10 differential LVDS outputs Guaranteed AC parameters over temperature and voltage: >1GHz fMAX <50ps within device skew <400ps tr/tf time Each bank includes a 2:1 input mux 2:1 mux input accepts LVDS and LVPECL Low jitter performance <1psRMS cycle-to-cycle jitter <1psPP total jitter 3.3V supply voltage Output enable function LVDS input includes internal 100Ω termination Available in a 64-Pin EPAD-TQFP

The SY89828L is a precision fanout buffer with 20 differential LVDS (Low Voltage Differential Swing) output pairs. The part is designed for use in low voltage 3.3V applications that require a large number of outputs to drive precisely aligned, ultra low-skew signals to their destination.The input is multiplexed from either LVDS or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK_SEL1 and CLK_SEL2 pins. The Output Enables (OE1 and OE2) are synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89828L features a low pin-to-pin skew of less than 50ps--performance previously unachievable in a standard product having such a high number of outputs.The SY89828L is available in a single space saving package, enabling a lower overall cost solution.

Additional Features

    • High-performance dual 1:10, 1GHz LVDS fanout buffer/translator
    • Two banks of 10 differential LVDS outputs
    • Guaranteed AC parameters over temperature and voltage:
      • >1GHz fMAX
      • <50ps within device skew
      • <400ps tr/tf time
    • Each bank includes a 2:1 input mux
    • 2:1 mux input accepts LVDS and LVPECL
    • Low jitter performance
      • <1psRMS cycle-to-cycle jitter
      • <1psPP total jitter
    • 3.3V supply voltage
    • Output enable function
    • LVDS input includes internal 100Ω termination
    • Available in a 64-Pin EPAD-TQFP
Supplier's Site Datasheet

Technical Specifications

  Microchip Technology, Inc.
Product Category Amplifier and Comparator Chips
Product Number SY89828L
Package Type ['TQFP']
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