The SY89823L is a high-performance bus clock driver with 22 differential High-Speed Transceiver Logic (HSTL), 1.5V compatible output pairs. The device is designed for use in low-voltage (3.3V/1.8V) applications that require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. The input is multiplexed from either HSTL or Low-Voltage Positive- Emitter-Coupled Logic (LVPECL) by the CLK_SEL pin.The Output Enable (OE) is synchronous and triple-buffered so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any potential of generating a runt clock pulse when the device is enabled/disabled, as can occur with an asynchronous control. The triple-buffering feature provides a threeclock delay from the time the OE input is asserted/de-asserted to when the clock appears at the outputs.The SY89823L features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.), performance previously unachievable in a standard product having such a high number of outputs. The SY89823L is available in a single, space-saving package, enabling a lower overall cost solution.
Additional Features
22 differential HSTL (low-voltage swing) output pairs
HSTL outputs drive 50Ω to ground with no offset voltage
3.3V core supply, 1.8V output supply for reduced power
LVPECL and HSTL inputs
Low part-to-part skew (200ps max.)
Low pin-to-pin skew (50ps max.)
Triple-buffered output enable (OE)
-40°C to +85°C temperature range
Available in a 64-pin EPAD-TQFP
The SY89823L is a high-performance bus clock driver with 22 differential High-Speed Transceiver Logic (HSTL), 1.5V compatible output pairs. The device is designed for use in low-voltage (3.3V/1.8V) applications that require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. The input is multiplexed from either HSTL or Low-Voltage Positive- Emitter-Coupled Logic (LVPECL) by the CLK_SEL pin.The Output Enable (OE) is synchronous and triple-buffered so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any potential of generating a runt clock pulse when the device is enabled/disabled, as can occur with an asynchronous control. The triple-buffering feature provides a threeclock delay from the time the OE input is asserted/de-asserted to when the clock appears at the outputs.The SY89823L features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.), performance previously unachievable in a standard product having such a high number of outputs. The SY89823L is available in a single, space-saving package, enabling a lower overall cost solution.
Additional Features
- 22 differential HSTL (low-voltage swing) output pairs
- HSTL outputs drive 50Ω to ground with no offset voltage
- 3.3V core supply, 1.8V output supply for reduced power
- LVPECL and HSTL inputs
- Low part-to-part skew (200ps max.)
- Low pin-to-pin skew (50ps max.)
- Triple-buffered output enable (OE)
- -40°C to +85°C temperature range
- Available in a 64-pin EPAD-TQFP
