The SY89809AL is a high-performance bus clock driver with nine differential High-Speed Transceiver Logic (HSTL) output pairs. The part is designed for use in low-voltage (3.3V/1.8V) applications, which require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. The input is multiplexed from either HSTL or Low-Voltage Positive-Emitter-Cou
pled Logic (LVPECL) by the CLK_SEL pin. The Output Enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state.This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89809AL features low pin-to-pin skew (15ps typical) and low part-to-part skew (100ps typical). The SY89809AL is available in a single space-saving package, enabling a lower overall cost solution.
Additional Features
3.3V core supply, 1.8V output supply for reduced power
LVPECL and HSTL inputs
Nine differential HSTL (low-voltage swing) output pairs
HSTL outputs drive 50Ω-to-ground with no offset voltage
750MHz maximum clock frequency
Low part-to-part skew (100ps typical)
Low pin-to-pin skew (15ps typical)
Available in 32-pin TQFP
The SY89809AL is a high-performance bus clock driver with nine differential High-Speed Transceiver Logic (HSTL) output pairs. The part is designed for use in low-voltage (3.3V/1.8V) applications, which require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. The input is multiplexed from either HSTL or Low-Voltage Positive-Emitter-Coupled Logic (LVPECL) by the CLK_SEL pin. The Output Enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state.This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89809AL features low pin-to-pin skew (15ps typical) and low part-to-part skew (100ps typical). The SY89809AL is available in a single space-saving package, enabling a lower overall cost solution.
Additional Features
- 3.3V core supply, 1.8V output supply for reduced power
- LVPECL and HSTL inputs
- Nine differential HSTL (low-voltage swing) output pairs
- HSTL outputs drive 50Ω-to-ground with no offset voltage
- 750MHz maximum clock frequency
- Low part-to-part skew (100ps typical)
- Low pin-to-pin skew (15ps typical)
- Available in 32-pin TQFP
