The SY88943V limiting post amplifier with its high gain and wide bandwidth is ideal for use as a post amplifier in fiber-optic receivers with data rates up to 2.5Gbps. Signals as small as 5mVp-p can be amplified to drive devices with PECL inputs. The SY88943V generates a chatter-free Signal Detect (SD) open collector TTL output.
The SY88943V incorporates a programmable level detect function to identify when the input signal has been lost. This information can be fed back to the EN input of the device to maintain stability under loss of signal condition. Using SDLVL pin, the sensitivity of the level detection can be adjusted. The SDLVL voltage can be set by connecting a resistor divider between VCC and VREF. Figure 3 and Figure 4 show the relationship between input level sensitivity and the voltage set on SDLVL. Figure 5 shows the relationship between input level sensitivity and resistor divider ratio.
The SD output is a TTL open collector output that requires a pull-up resistor for proper operation
Additional Features
3.3V and 5V power supply options
Up to 2.5Gbps operation
Low noise
Chatter-fee signal detect (SD) generation
Open collector TTL signal detect (SD) output
TTL EN input
Differential PECL inputs for data
Single power supply
Designed for use with Micrel-High-Bandwidt
h laser diode driver and controller
Available in a tiny (3mm) 10-pin MSOP
The SY88943V limiting post amplifier with its high gain and wide bandwidth is ideal for use as a post amplifier in fiber-optic receivers with data rates up to 2.5Gbps. Signals as small as 5mVp-p can be amplified to drive devices with PECL inputs. The SY88943V generates a chatter-free Signal Detect (SD) open collector TTL output.
The SY88943V incorporates a programmable level detect function to identify when the input signal has been lost. This information can be fed back to the EN input of the device to maintain stability under loss of signal condition. Using SDLVL pin, the sensitivity of the level detection can be adjusted. The SDLVL voltage can be set by connecting a resistor divider between VCC and VREF. Figure 3 and Figure 4 show the relationship between input level sensitivity and the voltage set on SDLVL. Figure 5 shows the relationship between input level sensitivity and resistor divider ratio.
The SD output is a TTL open collector output that requires a pull-up resistor for proper operation
Additional Features
- 3.3V and 5V power supply options
- Up to 2.5Gbps operation
- Low noise
- Chatter-fee signal detect (SD) generation
- Open collector TTL signal detect (SD) output
- TTL EN input
- Differential PECL inputs for data
- Single power supply
- Designed for use with Micrel-High-Bandwidth laser diode driver and controller
- Available in a tiny (3mm) 10-pin MSOP
