The SY88933V low-power limiting post amplifier is designed for use in fiber-optic receivers. The device connects to typical transimpedance amplifiers (TIAs). The linear signal output from TIAs can contain significant amounts of noise and may vary in amplitude over time. The SY88933V quantizes these signals and outputs PECL level waveforms. The SY88933V operates from a single +3.3V or +5V power supply, over temperatures ranging from -40°C to +85°C. With its wide bandwidth and high gain, signals with data rates up to 1.25Gbps and as small as 5mVp-p can be amplified to drive devices with PECL inputs. The SY88933V generates a TTL SD output. A programmable signal-detect level set pin (SDLVL) sets the sensitivity of the input amplitude detection. SD asserts high if the input amplitude rises above the threshold set by SDLVL and deasserts low otherwise. EN deasserts the true output signal without removing the input signal. Typically 4.6dB SD hysteresis is provided to prevent chattering.
Additional Features
Single 3.3V or 5V power supply
DC to 1.25Gbps operation
Low noise PECL data outputs
Chatter-free OC-TTL signal setect (SD) output with internal 6.75kΩ pull-up resistor
TTL EN input
Programmable SD level set (SDLVL)
Available in a tiny 10-pin MSOP (3mm) package
The SY88933V low-power limiting post amplifier is designed for use in fiber-optic receivers. The device connects to typical transimpedance amplifiers (TIAs). The linear signal output from TIAs can contain significant amounts of noise and may vary in amplitude over time. The SY88933V quantizes these signals and outputs PECL level waveforms. The SY88933V operates from a single +3.3V or +5V power supply, over temperatures ranging from -40°C to +85°C. With its wide bandwidth and high gain, signals with data rates up to 1.25Gbps and as small as 5mVp-p can be amplified to drive devices with PECL inputs. The SY88933V generates a TTL SD output. A programmable signal-detect level set pin (SDLVL) sets the sensitivity of the input amplitude detection. SD asserts high if the input amplitude rises above the threshold set by SDLVL and deasserts low otherwise. EN deasserts the true output signal without removing the input signal. Typically 4.6dB SD hysteresis is provided to prevent chattering.
Additional Features
- Single 3.3V or 5V power supply
- DC to 1.25Gbps operation
- Low noise PECL data outputs
- Chatter-free OC-TTL signal setect (SD) output with internal 6.75kΩ pull-up resistor
- TTL EN input
- Programmable SD level set (SDLVL)
- Available in a tiny 10-pin MSOP (3mm) package
