The SY54020R is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with active-low Enable (/EN) and Fail-Safe Input (FSI). The Enable is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. When this device is used as a clock fanout, disabling the downstream clock may reduce system power. FSI is a special circuit designed to sense the amplitude of the input signal and to latch the output when an invalid or no signal is present at the input. The SY54020R can process clock signals up to 2.5 GHz or data patterns up to 3.2Gbps.The differential input includes Micrel’s unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals as small as 100mV (200mVpp) without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an internal voltage reference is provided to bias the VT pin. The outputs are CML, with extremely fast rise/fall times guaranteed to be less than 100ps.The SY54020R operates from a 2.5V ±5% core supply and a 1.2V, 1.8V, or 2.5V ±5% output supply and is guaranteed over the full industrial temperature range (–40°C to +85°C).
Additional Features
1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with FSI
Active-low Enable (/EN) input to disable the outputs
Guaranteed AC performance over temperature and voltage:
DC-to- >3.2Gbps throughput
DC-to >2.5GHz Clock throughput
<400ps propagation delay (IN-to-Q)
<20ps within-device skew
<100ps rise/fall times
Ultra-low jitter design
<1psRMS cycle-to-cycle jitter
High-speed CML outputs
2.5V ±5% VCC, 1.2V/1.8V/2.5V ±5% VCCOpower supply operation
Industrial temperature range: -40°C to +85°C
Available in 16-pin (3mm x 3mm) QFN package
The SY54020R is a fully differential, low voltage 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with active-low Enable (/EN) and Fail-Safe Input (FSI). The Enable is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. When this device is used as a clock fanout, disabling the downstream clock may reduce system power. FSI is a special circuit designed to sense the amplitude of the input signal and to latch the output when an invalid or no signal is present at the input. The SY54020R can process clock signals up to 2.5 GHz or data patterns up to 3.2Gbps.The differential input includes Micrel’s unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals as small as 100mV (200mVpp) without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an internal voltage reference is provided to bias the VT pin. The outputs are CML, with extremely fast rise/fall times guaranteed to be less than 100ps.The SY54020R operates from a 2.5V ±5% core supply and a 1.2V, 1.8V, or 2.5V ±5% output supply and is guaranteed over the full industrial temperature range (–40°C to +85°C).
Additional Features
- 1.2V/1.8V/2.5V CML 1:4 Fanout Buffer with FSI
- Active-low Enable (/EN) input to disable the outputs
- Guaranteed AC performance over temperature and voltage:
- DC-to- >3.2Gbps throughput
- DC-to >2.5GHz Clock throughput
- <400ps propagation delay (IN-to-Q)
- <20ps within-device skew
- <100ps rise/fall times
- Ultra-low jitter design
- <1psRMS cycle-to-cycle jitter
- High-speed CML outputs
- 2.5V ±5% VCC, 1.2V/1.8V/2.5V ±5% VCCOpower supply operation
- Industrial temperature range: -40°C to +85°C
- Available in 16-pin (3mm x 3mm) QFN package
