The SY100EP14AU is a high-speed, 2GHz differential PECL/ECL 1:5 fanout buffer optimized for ultra-low skew applications. Within device skew is guaranteed to be less than 25ps over temperature and supply voltage. The wide supply voltage operation allows this fanout buffer to operate in 2.5V and 3.3V systems. A VBB reference is included for single-supply or AC-coupled PECL/ECL input applications, thus eliminating resistor networks. When interfacing to a single-ended or AC-coupled PECL/ECL input signal, connect the VBB pin to the unused /CLK pin, and bypass the pin to VCC through a 0.01µF capacitor. The SY100EP14AU features a 2:1 input MUX, making it an ideal solution for redundant clock switchover applications. If only one input pair is used, the other pair may be left floating. In addition, this device includes a synchronous enable pin that forces the outputs into a fixed logic state. Enable or disable state is initiated only after the outputs are in a LOW state, thus eliminating the possibility of a "runt" clock pulse. The SY100EP14AU I/O are fully differential and 100K ECL compatible. Differential 10K ECL logic can interface directly into the SY100EP14AU inputs.The SY100EP14AU is part of Micrel's high-speed clock synchronization family. For applications that require a different I/O combination, choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock generators.
Additional Features
Guaranteed AC parameters over temp/voltage: - >2GHz fMAX - <25ps within-device skew - <250ps tr/tf time - <550ps prop delay
2:1 Differential MUX input
Unique, patented MUX input isolation design minimizes adjacent channel crosstalk
Flexible supply voltage: 2.5V/3.3V
Wide operating temperature range: -40°C to +85°C
VBB reference for single-ended or AC-coupled PECL inputs
100K ECL compatible outputs
Inputs accept PECL/LVPECL/ECL/HSTL logic
75KΩ internal input pull-down resistors
Available in a 20-Pin TSSOP package
The SY100EP14AU is a high-speed, 2GHz differential PECL/ECL 1:5 fanout buffer optimized for ultra-low skew applications. Within device skew is guaranteed to be less than 25ps over temperature and supply voltage. The wide supply voltage operation allows this fanout buffer to operate in 2.5V and 3.3V systems. A VBB reference is included for single-supply or AC-coupled PECL/ECL input applications, thus eliminating resistor networks. When interfacing to a single-ended or AC-coupled PECL/ECL input signal, connect the VBB pin to the unused /CLK pin, and bypass the pin to VCC through a 0.01µF capacitor.
The SY100EP14AU features a 2:1 input MUX, making it an ideal solution for redundant clock switchover applications. If only one input pair is used, the other pair may be left floating. In addition, this device includes a synchronous enable pin that forces the outputs into a fixed logic state. Enable or disable state is initiated only after the outputs are in a LOW state, thus eliminating the possibility of a "runt" clock pulse.
The SY100EP14AU I/O are fully differential and 100K ECL compatible. Differential 10K ECL logic can interface directly into the SY100EP14AU inputs.The SY100EP14AU is part of Micrel's high-speed clock synchronization family. For applications that require a different I/O combination, choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock generators.
Additional Features
- Guaranteed AC parameters over temp/voltage: - >2GHz fMAX - <25ps within-device skew - <250ps tr/tf time - <550ps prop delay
- 2:1 Differential MUX input
- Unique, patented MUX input isolation design minimizes adjacent channel crosstalk
- Flexible supply voltage: 2.5V/3.3V
- Wide operating temperature range: -40°C to +85°C
- VBB reference for single-ended or AC-coupled PECL inputs
- 100K ECL compatible outputs
- Inputs accept PECL/LVPECL/ECL/HSTL logic
- 75KΩ internal input pull-down resistors
- Available in a 20-Pin TSSOP package
