The SY10/100E111 are low skew 1-to-9 differential drivers designed for clock distribution in new, highperformance ECL systems. They accept one differential or single-ended input, with V,sub>BB used for single-ended operation. The signal is fanned out to nine identical differential outputs. An enable input is also provided such that a logic HIGH disables the device by forcing all Q outputs LOW and all /Q outputs HIGH. The device is specifically designed and produced for low skew. The interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. Wafer characterization and process control ensure consistent distribution of propagation delay from lot to lot. Since the E111 shares a common set of "basic" processing with the other members of the ECLinPS™ family, wafer characterization at the point of device personalization allows for tighter control of parameters, including propagation delay. To ensure that the skew specification is met, it is necessary that both sides of the differential output are terminated into 50Ω, even if only one side is being used. ln most applications, all nine differential pairs will be used and, therefore, terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO as the pair(s) being used on that side) in order to maintain minimum skew. The VBB output is intended for use as a reference voltage for single-ended reception of ECL signals to that device only. When using VBB for this purpose, it is recommended that VBB is decoupled to VCC via a 0.01µF capacitor.
Additional Features
Low skew
Extended 100E VEE range of -4.2V to -5.5V
Guaranteed skew limits
Differential design
VBB output
Enable input
Fully compatible with industry standard 10KH, 100K I/O levels
75KΩ input pulldown resistors
Fully compatible with ON Semiconductor MC10E/100E111
Available in 28-pin PLCC package
The SY10/100E111 are low skew 1-to-9 differential drivers designed for clock distribution in new, highperformance ECL systems. They accept one differential or single-ended input, with V,sub>BB used for single-ended operation. The signal is fanned out to nine identical differential outputs. An enable input is also provided such that a logic HIGH disables the device by forcing all Q outputs LOW and all /Q outputs HIGH.
The device is specifically designed and produced for low skew. The interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. Wafer characterization and process control ensure consistent distribution of propagation delay from lot to lot. Since the E111 shares a common set of "basic" processing with the other members of the ECLinPS™ family, wafer characterization at the point of device personalization allows for tighter control of parameters, including propagation delay.
To ensure that the skew specification is met, it is necessary that both sides of the differential output are terminated into 50Ω, even if only one side is being used. ln most applications, all nine differential pairs will be used and, therefore, terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same VCCO as the pair(s) being used on that side) in order to maintain minimum skew.
The VBB output is intended for use as a reference voltage for single-ended reception of ECL signals to that device only. When using VBB for this purpose, it is recommended that VBB is decoupled to VCC via a 0.01µF capacitor.
Additional Features
- Low skew
- Extended 100E VEE range of -4.2V to -5.5V
- Guaranteed skew limits
- Differential design
- VBB output
- Enable input
- Fully compatible with industry standard 10KH, 100K I/O levels
- 75KΩ input pulldown resistors
- Fully compatible with ON Semiconductor MC10E/100E111
- Available in 28-pin PLCC package
