Microchip Technology, Inc. Switchtec PFX Fanout 80xG3 PCIe Switch PM8535

The Switchtec PM8535 PFX Gen 3 fanout PCIe switch is the industry's highest density, lowest power, high reliability PCIe Base Specification 3.1-compliant switch for data center, communications, defense, and industrial applications. With simple hardware configuration and advanced diagnostics and debug capabilities, the PM8535 enable PCIe solutions for a wide variety of systems from JBOFs (Just a Bunch Of Flash) to general purpose applications requiring low power and high-reliability PCIe switching. Additional Features Most flexible per port bifurcation in the industry 80 lanes, 40 ports and 40 NTBs 20 virtual switch partitions for efficient use of system resources Advanced error containment and surprise-plug and unplug support to prevent system crashes Advanced diagnostics and debug features to identify, diagnose and fix problems SRIS for cabled PCIe and lower cost system designs HIgh Performance Non-Blocking Switch Up to 174 GB/s switching capacity Logical Non-Transparent (NT) interconnect allows for larger topologies (up to 256 masters) Supports 1+1 and N+1 failover mechanisms NT address translation using direct windows and multiple sub-windows per BAR Supports multicast groups per port Error Containment Advanced Error Reporting (AER) on all ports Downstream Port Containment (DPC) on all downstream ports Poisoned TLP blocking Completion Timeout Synthesis (CTS) to prevent an error state in an upstream host due to incomplete non-posted transactions Hot- and surprise-plug controllers per port GPIOs configurable for different cable/connector standards PCIe Interfaces Passive, managed, and optical cables SFF-8644, SFF-8643, SFF-8639, OCuLink, and other connectors SHPC-enabled slot and edge connectors Diagnostics and Debug Transaction Layer Packet (TLP) generator for testing and debugging of links and error handling Real-time eye capture Any-to-any port mirroring for debug purposes External loopback at PHY and TLP layers Errors, statistics, performance, and TLP latency counters Peripheral I/O Interfaces Up to 11 Two-Wire Interfaces (TWIs) with SMBus support Up to 2 SFF-8485-compliant SGPIO ports Up to 109 parallel GPIO pins Up to 4 UARTs JTAG and EJTAG interface High-speed I/O PCIe Gen 3 8 GT/s Supports PCIe-compliant link training and manual PHY configuration Power Management Active State Power Management (ASPM) Software controlled power management Chiplink Diagnostic Tools Extensive debug, diagnostics, configuration, and analysis tools with an intuitive GUI Access to configuration data, management capabilities, and signal integrity analysis tools (such as real-time eye capture) Connects to device over in-band PCIe or sideband signals (UART, TWI, and EJTAG) Evaluation PM5461-KIT—PSX/PFX 96/80/64xG3, 1-Slot, 16 HD Evaluation Kit