PIC24F 16-bit Microcontroller featuring up to 256KB of ECC Flash, 16KB of RAM and eXtreme Low Power. It has 12bit ADC at 200ksps with up to 14 analog inputs, 3 comparators and CTMU for touch applications. Available in 28 pin, 44 pin and 48 pin packages. This family is ideally suited for general purpose applications.
Additional Features
CPU
Modified Harvard Architecture
Up to 16 MIPS Operation @ 32 MHz
8 MHz Internal Oscillator:
96 MHz PLL option
Multiple clock divide options
Fast start-up
17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
32-Bit by 16-Bit Hardware Divider
16 x 16-Bit Working Register Array
C Compiler Optimized Instruction Set Architecture
Two Address Generation Units for Separate Read and Write Addressing of Data Memory
Analog Features
Up to 14-Channel, Software Selectable, 10/12-Bit Analog-to-Digital Converter:
12-bit, 200K samples/second conversion rate (single Sample-and-Hold)
Sleep mode operation
Charge pump for operating at lower AVDD
Band gap reference input feature
Windowed threshold compare feature
Auto-scan feature
Three Analog Comparators with Input Multiplexing
LVD Interrupt Above/Below Programmable VLVD Level
Charge Time Measurement Unit (CTMU):
Allows measurement of capacitance and time
Operational in Sleep
eXtreme Low-Power Features
Sleep and Idle modes Selectively Shut Down Peripherals and/or Core for Substantial Power Reduction and Fast Wake-up
Doze mode Allows CPU to Run at a Lower Clock Speed than Peripherals
Alternate Clock modes Allow On-the-Fly Switching to a Lower Clock Speed for Selective Power Reduction
PIC24F 16-bit Microcontroller featuring up to 256KB of ECC Flash, 16KB of RAM and eXtreme Low Power. It has 12bit ADC at 200ksps with up to 14 analog inputs, 3 comparators and CTMU for touch applications. Available in 28 pin, 44 pin and 48 pin packages. This family is ideally suited for general purpose applications.
Additional Features
- CPU
- Modified Harvard Architecture
- Up to 16 MIPS Operation @ 32 MHz
- 8 MHz Internal Oscillator:
- 96 MHz PLL option
- Multiple clock divide options
- Fast start-up
- 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
- 32-Bit by 16-Bit Hardware Divider
- 16 x 16-Bit Working Register Array
- C Compiler Optimized Instruction Set Architecture
- Two Address Generation Units for Separate Read and Write Addressing of Data Memory
- Analog Features
- Up to 14-Channel, Software Selectable, 10/12-Bit Analog-to-Digital Converter:
- 12-bit, 200K samples/second conversion rate (single Sample-and-Hold)
- Sleep mode operation
- Charge pump for operating at lower AVDD
- Band gap reference input feature
- Windowed threshold compare feature
- Auto-scan feature
- Three Analog Comparators with Input Multiplexing
- LVD Interrupt Above/Below Programmable VLVD Level
- Charge Time Measurement Unit (CTMU):
- Allows measurement of capacitance and time
- Operational in Sleep
- eXtreme Low-Power Features
- Sleep and Idle modes Selectively Shut Down Peripherals and/or Core for Substantial Power Reduction and Fast Wake-up
- Doze mode Allows CPU to Run at a Lower Clock Speed than Peripherals
- Alternate Clock modes Allow On-the-Fly Switching to a Lower Clock Speed for Selective Power Reduction
