Additional Features
40-pin packaging
Baseline Core with 33 Instructions, 2 Stack Levels
All single-cycle Instructions except for program branches which are two cycles
12-bit wide instructions
8-bit wide data path
Low power (100nA) sleep current
One 8-bit timer (TMR0)
Watchdog timer (WDT)
In Circuit Serial Programming™ (ICSP™) capability
Programmable code protection
Microchip Technology, Inc.
Done
Datasheet
Description
Additional Features
40-pin packaging
Baseline Core with 33 Instructions, 2 Stack Levels
All single-cycle Instructions except for program branches which are two cycles
12-bit wide instructions
8-bit wide data path
Low power (100nA) sleep current
One 8-bit timer (TMR0)
Watchdog timer (WDT)
In Circuit Serial Programming™ (ICSP™) capability
Programmable code protection
Additional Features
40-pin packaging
Baseline Core with 33 Instructions, 2 Stack Levels
All single-cycle Instructions except for program branches which are two cycles
12-bit wide instructions
8-bit wide data path
Low power (100nA) sleep current
One 8-bit timer (TMR0)
Watchdog timer (WDT)
In Circuit Serial Programming™ (ICSP™) capability
Programmable code protection
Additional Features
40-pin packaging
Baseline Core with 33 Instructions, 2 Stack Levels
All single-cycle Instructions except for program branches which are two cycles
