The MDB1900ZC is a true zero delay buffer with fully integrated high-performance, low-power, and low phase noise programmable PLL.The MDB1900ZC is capable of distributing the reference clocks for PCIe (Gen1/Gen2/Gen3), SATA, ESI, SAS, SMI, and Intel® Quickpath Interconnect (QPI). The MDB1900ZC works in conjunction with a CK410B+, CK509B, or CK420BQ clock synthesizer to provide reference clocks to multiple agents.The MDB1900ZC is designed for Intel’s DB1900Z specification with the exception that the zero delay buffer feedback path is inside the IC and does not need to be built onto the PCB.
Additional Features
Supports zero delay (0ps) buffer mode for 100MHz and 133MHz clock frequencies.
Internal feedback path for zero delay (PLL) mode
Zero delay (PLL) mode can filter jitter in incoming clock
Selectable PLL bandwidth for PLL mode
Supports fanout buffer mode for clock frequencies between 0MHz and 250MHz
Differential input reference with HCSL logic (0V ~ 0.7V)
Nineteen differential HCSL-compatible clock output pairs
Eight dedicated OE# pins to control their assigned output. Glitch free assertion/de-asserti
on.
Spread spectrum modulation tolerant for EMI reduction
SMBus interface for controlling output properties (enable/disable and delay tuning)
Disabled outputs in power-down mode for maximum power savings
Nine selectable SMBus addresses so multiple devices can share the same SMBus
3.3V or 2.5V operation
Commercial temperature range (0°C to +70°C)
72-pin 10mm × 10mm QFN package
GREEN, RoHS, and PFOS compliant
The MDB1900ZC is a true zero delay buffer with fully integrated high-performance, low-power, and low phase noise programmable PLL.The MDB1900ZC is capable of distributing the reference clocks for PCIe (Gen1/Gen2/Gen3), SATA, ESI, SAS, SMI, and Intel® Quickpath Interconnect (QPI). The MDB1900ZC works in conjunction with a CK410B+, CK509B, or CK420BQ clock synthesizer to provide reference clocks to multiple agents.The MDB1900ZC is designed for Intel’s DB1900Z specification with the exception that the zero delay buffer feedback path is inside the IC and does not need to be built onto the PCB.
Additional Features
- Supports zero delay (0ps) buffer mode for 100MHz and 133MHz clock frequencies.
- Internal feedback path for zero delay (PLL) mode
- Zero delay (PLL) mode can filter jitter in incoming clock
- Selectable PLL bandwidth for PLL mode
- Supports fanout buffer mode for clock frequencies between 0MHz and 250MHz
- Differential input reference with HCSL logic (0V ~ 0.7V)
- Nineteen differential HCSL-compatible clock output pairs
- Eight dedicated OE# pins to control their assigned output. Glitch free assertion/de-assertion.
- Spread spectrum modulation tolerant for EMI reduction
- SMBus interface for controlling output properties (enable/disable and delay tuning)
- Disabled outputs in power-down mode for maximum power savings
- Nine selectable SMBus addresses so multiple devices can share the same SMBus
- 3.3V or 2.5V operation
- Commercial temperature range (0°C to +70°C)
- 72-pin 10mm × 10mm QFN package
- GREEN, RoHS, and PFOS compliant
