The HV7224 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. It is especially suitable for use as a symmetric row driver in AC thin-film electroluminescent (ACTFEL) displays. When the data reset pin (DRIOA/DRIOB) is at logic high, it will reset all the outputs of the internal shift register to zero. At the same time, the output of the shift register will start shifting a logic high from the least significant bit to the most significant bit. The DRIOA/DRIOB can be triggered at any time. The DIR and SHIFT pins control the direction of data shift through the device. When DIR is at logic high, DRIOA is the input and DRIOB is the output. When DIR is grounded, DRIOB is the input and the DRIOA is the output. See the Output Sequence Operation Table for output sequence. The POL and OE pins perform the polarity select and output enable function respectively. Data is loaded on the low to high transition of the clock. A logic high will cause the output to swing to VPP if POL is high, or to GND if POL is low. All outputs will be in High-Z state if OE is at logic high. Data output buffers are provided for cascading devices.
Additional Features
HVCMOS® technology
Symmetric row drive (reduces latent imaging in ACTFEL displays)
Output voltage up to +240V
Low power level shifting
Source/sink current minimum 70mA
Shift register speed 3.0MHz
Pin-programmable shift direction (DIR, SHIFT)
The HV7224 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. It is especially suitable for use as a symmetric row driver in AC thin-film electroluminescent (ACTFEL) displays. When the data reset pin (DRIOA/DRIOB) is at logic high, it will reset all the outputs of the internal shift register to zero. At the same time, the output of the shift register will start shifting a logic high from the least significant bit to the most significant bit. The DRIOA/DRIOB can be triggered at any time. The DIR and SHIFT pins control the direction of data shift through the device. When DIR is at logic high, DRIOA is the input and DRIOB is the output. When DIR is grounded, DRIOB is the input and the DRIOA is the output. See the Output Sequence Operation Table for output sequence. The POL and OE pins perform the polarity select and output enable function respectively. Data is loaded on the low to high transition of the clock. A logic high will cause the output to swing to VPP if POL is high, or to GND if POL is low. All outputs will be in High-Z state if OE is at logic high. Data output buffers are provided for cascading devices.
Additional Features
- HVCMOS® technology
- Symmetric row drive (reduces latent imaging in ACTFEL displays)
- Output voltage up to +240V
- Low power level shifting
- Source/sink current minimum 70mA
- Shift register speed 3.0MHz
- Pin-programmable shift direction (DIR, SHIFT)
