The HV57908 is a low voltage serial to high voltage parallel converter with push-pull outputs. The device has been designed for use as a driver for EL displays. It can also be used in any application requiring multiple output high voltage current sourcing and sinking capability such as driving plasma panels, vacuum fluorescent displays, or large matrix LCD displays. The device consists of a 64-bit shift register, 64 latches and control logic to perform the polarity select and blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the polarity and blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to GND, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift registers to the latches occurs when the LE input is high. The data in the latches is stored when the LE is low.
Additional Features
HVCMOS® technology
5.0V CMS Logic
Output voltage up to +80V
Low power level shifting
8.0MHz data rate
Latched data outputs
Forward and reverse shifting options (DIR pin)
Diode to VPP allows efficient power recovery
Outputs may be hot switched
The HV57908 is a low voltage serial to high voltage parallel converter with push-pull outputs. The device has been designed for use as a driver for EL displays. It can also be used in any application requiring multiple output high voltage current sourcing and sinking capability such as driving plasma panels, vacuum fluorescent displays, or large matrix LCD displays. The device consists of a 64-bit shift register, 64 latches and control logic to perform the polarity select and blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the polarity and blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to GND, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift registers to the latches occurs when the LE input is high. The data in the latches is stored when the LE is low.
Additional Features
- HVCMOS® technology
- 5.0V CMS Logic
- Output voltage up to +80V
- Low power level shifting
- 8.0MHz data rate
- Latched data outputs
- Forward and reverse shifting options (DIR pin)
- Diode to VPP allows efficient power recovery
- Outputs may be hot switched
