The HV57009 is a low-voltage serial to high-voltage parallel converter with P-channel open drain outputs. This device has been designed for use as a driver for plasma panels. The device has two parallel 32-bit shift registers, permitting data rates twice the speed of one (they are clocked together). There are also 64 latches and control logic to perform the blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to VSS, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), or the BL (blanking) inputs. Transfer of data from the shift registers to latches occurs when the LE input is high. The data in the latches is stored when LE is low. The HV570 has 64 channels of output constant current sourcing capability. They are adjustable from 0.1 to 2.0mA through one external resistor or a current source.
Additional Features
HVCMOS® technology
5.0V CMOS Logic
Output voltage up to -85V
Output current source control
16MHz equivalent data rate
Latched data outputs
Forward and reverse shifting options (DIR pin)
Diode to VDD allows efficient power recovery
The HV57009 is a low-voltage serial to high-voltage parallel converter with P-channel open drain outputs. This device has been designed for use as a driver for plasma panels. The device has two parallel 32-bit shift registers, permitting data rates twice the speed of one (they are clocked together). There are also 64 latches and control logic to perform the blanking of the outputs. HVOUT1 is connected to the first stage of the first shift register through the blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to VSS, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), or the BL (blanking) inputs. Transfer of data from the shift registers to latches occurs when the LE input is high. The data in the latches is stored when LE is low. The HV570 has 64 channels of output constant current sourcing capability. They are adjustable from 0.1 to 2.0mA through one external resistor or a current source.
Additional Features
- HVCMOS® technology
- 5.0V CMOS Logic
- Output voltage up to -85V
- Output current source control
- 16MHz equivalent data rate
- Latched data outputs
- Forward and reverse shifting options (DIR pin)
- Diode to VDD allows efficient power recovery
