IPC International, Inc. Implementation of Flip Chip & Chip Scale Technology J-STD-012

Description
DESCRIPTION This informative document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include design considerations, assembly processes, technology choices, application and reliability data. Chip packaging variations include flip chip, HDI, micro BGA, micro SMT and SLICC. Also provides general information on implementing flip chip and chip scale technologies for creating multichip modules, I/C cards, memory cards and very dense surface mount assemblies. Developed by IPC, EIA, MCNC and Sematech. 113 Pages. Released January 1996.
Description
DESCRIPTION This informative document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include design considerations, assembly processes, technology choices, application and reliability data. Chip packaging variations include flip chip, HDI, micro BGA, micro SMT and SLICC. Also provides general information on implementing flip chip and chip scale technologies for creating multichip modules, I/C cards, memory cards and very dense surface mount assemblies. Developed by IPC, EIA, MCNC and Sematech. 113 Pages. Released January 1996.

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Implementation of Flip Chip & Chip Scale Technology - J-STD-012 - IPC International, Inc.
Bannockburn, IL, United States
Implementation of Flip Chip & Chip Scale Technology
J-STD-012
Implementation of Flip Chip & Chip Scale Technology J-STD-012
DESCRIPTION This informative document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include design considerations, assembly processes, technology choices, application and reliability data. Chip packaging variations include flip chip, HDI, micro BGA, micro SMT and SLICC. Also provides general information on implementing flip chip and chip scale technologies for creating multichip modules, I/C cards, memory cards and very dense surface mount assemblies. Developed by IPC, EIA, MCNC and Sematech. 113 Pages. Released January 1996.

DESCRIPTION
This informative document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include design considerations, assembly processes, technology choices, application and reliability data. Chip packaging variations include flip chip, HDI, micro BGA, micro SMT and SLICC. Also provides general information on implementing flip chip and chip scale technologies for creating multichip modules, I/C cards, memory cards and very dense surface mount assemblies. Developed by IPC, EIA, MCNC and Sematech. 113 Pages. Released January 1996.

Supplier's Site
Implementation of Flip Chip & Chip Scale Technology - J-STD-012 - IPC International, Inc.
Bannockburn, IL, United States
Implementation of Flip Chip & Chip Scale Technology
J-STD-012
Implementation of Flip Chip & Chip Scale Technology J-STD-012
This informative document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include design considerations, assembly processes, technology choices, application and reliability data.

This informative document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include design considerations, assembly processes, technology choices, application and reliability data.

Supplier's Site

Technical Specifications

  IPC International, Inc.
Product Category Standards and Technical Documents
Product Number J-STD-012
Product Name Implementation of Flip Chip & Chip Scale Technology
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