Integrated Device Technology 8K x 9 DualAsync FIFO, 3.3V 72V85L20PA

Description
The 72V85 is a dual- FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/recepti on error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.
  • 8K x 9 DualAsync FIFO, 3.3V - 72V85L20PA - Integrated Device Technology
    Integrated Device Technology
Datasheet
Description
The 72V85 is a dual- FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/recepti on error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.
Datasheet

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8K x 9 DualAsync FIFO, 3.3V - 72V85L20PA - Integrated Device Technology
Integrated Device Technology
San Jose, CA, USA
8K x 9 DualAsync FIFO, 3.3V
72V85L20PA
8K x 9 DualAsync FIFO, 3.3V 72V85L20PA
The 72V85 is a dual- FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/recepti on error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.

The 72V85 is a dual- FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 72V85L20PA
Product Name 8K x 9 DualAsync FIFO, 3.3V
Memory Category FIFO
Logic Family TTL
Access Time 20 ns
Operating Temperature 0 to 70 C (32 to 158 F)
Density 72 kbits
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