Integrated Device Technology 1K x 18 SyncFIFO, 3.3V 72V225L10PFG8

Description
The 72V225 is a 1K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72225 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock( RCLK ) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.
Datasheet
Description
The 72V225 is a 1K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72225 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock( RCLK ) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.
Datasheet

Suppliers

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1K x 18 SyncFIFO, 3.3V - 72V225L10PFG8 - Integrated Device Technology
San Jose, CA, USA
1K x 18 SyncFIFO, 3.3V
72V225L10PFG8
1K x 18 SyncFIFO, 3.3V 72V225L10PFG8
The 72V225 is a 1K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72225 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock( RCLK ) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.

The 72V225 is a 1K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72225 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock( RCLK ) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 72V225L10PFG8
Product Name 1K x 18 SyncFIFO, 3.3V
Memory Category FIFO
Logic Family TTL
Data Rate 100 MHz
Operating Temperature 0 to 70 C (32 to 158 F)
Density 18 kbits
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