Integrated Device Technology 512K x 9 SuperSync FIFO, 3.3V 72V2111L15PFGI

Description
The 72V2111 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin ( FS ) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK , is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)
Datasheet
Description
The 72V2111 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin ( FS ) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK , is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)
Datasheet

Suppliers

Company
Product
Description
Supplier Links
512K x 9 SuperSync FIFO, 3.3V - 72V2111L15PFGI - Integrated Device Technology
San Jose, CA, USA
512K x 9 SuperSync FIFO, 3.3V
72V2111L15PFGI
512K x 9 SuperSync FIFO, 3.3V 72V2111L15PFGI
The 72V2111 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin ( FS ) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK , is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)

The 72V2111 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin ( FS ) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK , is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.)

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 72V2111L15PFGI
Product Name 512K x 9 SuperSync FIFO, 3.3V
Memory Category FIFO
Logic Family TTL
Data Rate 66 MHz
Operating Temperature -40 to 85 C (-40 to 185 F)
Density 4096 kbits
Unlock Full Specs
to access all available technical data

Similar Products

FIFOs Memory - SN74ACT7200L20NP - Quarktwin Technology Ltd.
Specs
Operating Temperature 0 to 70 C (32 to 158 F)
Density 2 kbits
Package Type DIP; 28-DIP (0.300\", 7.62mm)
View Details
SDRAM - 2420776 - RS Components, Ltd.
RS Components, Ltd.
Specs
Memory Category DRAM Chip
Access Time 0.4000 ns
Number of Words 64000 k
View Details
Memory - AS4C1259 - Micross Components, Inc.
Micross Components, Inc.
Specs
Memory Category DRAM; DRAM Chip
Access Time 100 to 150 ns
Operating Temperature -55 to 125 C (-67 to 257 F)
View Details