Integrated Device Technology 256 x 18 SyncFIFO, 3.3V 72V205L20TF8

Description
The 72V205 is a 256 x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72205 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock( RCLK ) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.
Datasheet
Description
The 72V205 is a 256 x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72205 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock( RCLK ) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.
Datasheet

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256 x 18 SyncFIFO, 3.3V - 72V205L20TF8 - Integrated Device Technology
San Jose, CA, USA
256 x 18 SyncFIFO, 3.3V
72V205L20TF8
256 x 18 SyncFIFO, 3.3V 72V205L20TF8
The 72V205 is a 256 x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72205 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock( RCLK ) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.

The 72V205 is a 256 x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72205 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock( RCLK ) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 72V205L20TF8
Product Name 256 x 18 SyncFIFO, 3.3V
Memory Category FIFO
Logic Family TTL
Data Rate 50 MHz
Operating Temperature 0 to 70 C (32 to 158 F)
Density 4 kbits
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