Integrated Device Technology 8K x 9 AsyncFIFO, 3.3V 72V05L25JGI

Description
The 72V05 is a 8K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit ( RT ) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW . It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.
Datasheet
Description
The 72V05 is a 8K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit ( RT ) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW . It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.
Datasheet

Suppliers

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Product
Description
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8K x 9 AsyncFIFO, 3.3V - 72V05L25JGI - Integrated Device Technology
San Jose, CA, USA
8K x 9 AsyncFIFO, 3.3V
72V05L25JGI
8K x 9 AsyncFIFO, 3.3V 72V05L25JGI
The 72V05 is a 8K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit ( RT ) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW . It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.

The 72V05 is a 8K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit ( RT ) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW . It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 72V05L25JGI
Product Name 8K x 9 AsyncFIFO, 3.3V
Memory Category FIFO
Logic Family TTL
Access Time 25 ns
Operating Temperature -40 to 85 C (-40 to 185 F)
Density 72 kbits
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