Integrated Device Technology 2K x 9 DualSync FIFO, 5.0V 72831L15PFI8

Description
The 72831 is a 2K x 9 dual synchronous (clocked) FIFO . The device is functionally equivalent to two 72231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72831 architecture lends itself to many flexible configurations such as: 2-level priority data buffering, Bidirectional operation, Width expansion and Depth expansion.
Datasheet
Description
The 72831 is a 2K x 9 dual synchronous (clocked) FIFO . The device is functionally equivalent to two 72231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72831 architecture lends itself to many flexible configurations such as: 2-level priority data buffering, Bidirectional operation, Width expansion and Depth expansion.
Datasheet

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2K x 9 DualSync FIFO, 5.0V - 72831L15PFI8 - Integrated Device Technology
San Jose, CA, USA
2K x 9 DualSync FIFO, 5.0V
72831L15PFI8
2K x 9 DualSync FIFO, 5.0V 72831L15PFI8
The 72831 is a 2K x 9 dual synchronous (clocked) FIFO . The device is functionally equivalent to two 72231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72831 architecture lends itself to many flexible configurations such as: 2-level priority data buffering, Bidirectional operation, Width expansion and Depth expansion.

The 72831 is a 2K x 9 dual synchronous (clocked) FIFO . The device is functionally equivalent to two 72231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72831 architecture lends itself to many flexible configurations such as: 2-level priority data buffering, Bidirectional operation, Width expansion and Depth expansion.

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Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 72831L15PFI8
Product Name 2K x 9 DualSync FIFO, 5.0V
Memory Category FIFO
Logic Family TTL
Data Rate 66 MHz
Operating Temperature -40 to 85 C (-40 to 185 F)
Density 18 kbits
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