Integrated Device Technology 256 x 18 SyncFIFO, 5.0V 72205LB10PFG8

Description
The 72205 is a 256 x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique.
Datasheet
Description
The 72205 is a 256 x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique.
Datasheet

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256 x 18 SyncFIFO, 5.0V - 72205LB10PFG8 - Integrated Device Technology
San Jose, CA, USA
256 x 18 SyncFIFO, 5.0V
72205LB10PFG8
256 x 18 SyncFIFO, 5.0V 72205LB10PFG8
The 72205 is a 256 x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique.

The 72205 is a 256 x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique.

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Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 72205LB10PFG8
Product Name 256 x 18 SyncFIFO, 5.0V
Memory Category FIFO
Logic Family TTL
Data Rate 100 MHz
Operating Temperature 0 to 70 C (32 to 158 F)
Density 4 kbits
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