The 71124 5V CMOS SRAM is organized as 128K x 8. The JEDEC centerpower/ GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71124 are TTL -compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.
| Integrated Device Technology | |
|---|---|
| Product Category | Memory Chips |
| Product Number | 71124S12YG |
| Product Name | 5.0V 128K x 8 Asynchronous Static RAM Center Pwr & Gnd Pinout |
| Memory Category | SRAM Chip |
| Access Time | 12 ns |
| Operating Temperature | 0 to 70 C (32 to 158 F) |
| Density | 1024 kbits |
| Number of Words | 128 k |
