Integrated Device Technology 256K x 36 Synchronous Bank-Switchable Dual-Port SRAM 70V7519S133BC

Description
The 70V7519 is a high-speed 256K x 36 (9Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 4Kx36 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 4Kx36 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1 , permits the on-chip circuitry of each port to enter a very low standby power mode.
Datasheet
Description
The 70V7519 is a high-speed 256K x 36 (9Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 4Kx36 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 4Kx36 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1 , permits the on-chip circuitry of each port to enter a very low standby power mode.
Datasheet

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256K x 36 Synchronous Bank-Switchable Dual-Port SRAM - 70V7519S133BC - Integrated Device Technology
San Jose, CA, USA
256K x 36 Synchronous Bank-Switchable Dual-Port SRAM
70V7519S133BC
256K x 36 Synchronous Bank-Switchable Dual-Port SRAM 70V7519S133BC
The 70V7519 is a high-speed 256K x 36 (9Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 4Kx36 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 4Kx36 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1 , permits the on-chip circuitry of each port to enter a very low standby power mode.

The 70V7519 is a high-speed 256K x 36 (9Mbit) synchronous Bank-Switchable Dual-Ported SRAM is organized into 64 independent 4Kx36 banks and has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 4Kx36 memory block not already accessed by the other port. An automatic power down feature, controlled by CE0 and CE1 , permits the on-chip circuitry of each port to enter a very low standby power mode.

Supplier's Site Datasheet

Technical Specifications

  Integrated Device Technology
Product Category Memory Chips
Product Number 70V7519S133BC
Product Name 256K x 36 Synchronous Bank-Switchable Dual-Port SRAM
Memory Category DPRAM; SRAM Chip
Logic Family TTL
Data Rate 133 MHz
Operating Temperature 0 to 70 C (32 to 158 F)
Density 9216 kbits
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