DIODES Incorporated Application Specific Clock/Timing PI6C20400AHE

The PI6C20400AHE is a PCIe® 2.0 compliant differential clock buffer designed for high-speed, low-noise applications. It features four pairs of differential clock outputs, which can operate with or without a phase-locked loop (PLL). The device supports a maximum output frequency of 400 MHz in bypass mode and 100 MHz in PLL mode. It has low skew of less than 50 ps and low jitter of less than 50 ps cycle-to-cycle, with an additive RMS phase jitter of less than 1 ps. Control of the clock outputs is managed through input selection pins, including SRC_STOP#, PWRDWN#, and SMBus interfaces for output enable and tristate control. The device operates at a supply voltage of 3.3V and is available in both 28-pin SSOP and TSSOP packages. It is fully RoHS compliant and free from halogens and antimony, making it suitable for environmentally conscious designs. This product is particularly relevant for engineers working on PCIe® chipset applications requiring precise clock distribution.