Cypress Semiconductor Corp. Asynchronous SRAM

Ultra-Reliable Asynchronous SRAMs Click to Enlarge With the performance to serve a wide variety of high reliability industrial, communication, data processing, medical, consumer and military applications, Fast and Micropower (MoBL®) SRAM devices are available with on-chip ECC. These devices are form-fit-function compatible with older generation Asynchronous SRAMs. This allows you to improve system reliability without investing in PCB re-design. High reliability: Soft-Error Rate < 0.1FIT/Mbit ERR pin to indicate single-bit errors Density options: 4-Mbit, 8-Mbit, 16-Mbit Fast access time: 10ns (FAST) Ultra-low standby current: 8.7μA (4-Mbit MoBL®) Bus-width configurations: x8, x16 and x32 Wide operating voltage range: 1.8-5.0V Industrial and Automotive temperature grades PowerSnooze„¢ Click to Enlarge Cypress is the first SRAM manufacturer to offer a new family of devices that combines the access time of Fast Asynchronous SRAM with a unique ultra-low-power sleep mode (PowerSnooze„¢). Fast SRAM with PowerSnooze eliminates the tradeoff between performance and power consumption in Asynchronous SRAM applications. In this new family of devices, the best features of existing family of products are achieved through the provision of a novel ultra-low-power sleep mode called PowerSnooze. PowerSnooze is an additional operating mode to standard Asynchronous SRAM operating modes (Active, Standby, and Data-Retention). Deep sleep pin (DS#) enables switching of the device between the high performance active mode and the ultra-low-power PowerSnooze mode. With deep sleep current as low as 15 μA on 4-Mbit devices, Fast SRAM with PowerSnooze combines the best features of Fast and Micropower SRAM in a single device. Asynchronous SRAM Technology EnhancementsError Correcting Code (ECC) Cypress™s latest generation Asynchronous SRAM devices use (38,32) hamming code ECC for single-bit error detection and correction. The hardware ECC block in Cypress™ ultra-reliable Asynchronous SRAMs performs all ECC related functions in line, without user intervention. Multi-bit Interleaving Higher energy extraterrestrial radiation can flip multiple adjacent bits, leading to multi-bit errors. The single-bit error detection and correction capability of Error Correcting Code is supplemented by a bit-interleaving scheme to prevent the occurrence of multi-bit errors. Together, these features provide significant improvement in Soft Error Rate (SER) performance, resulting in industry leading FIT rates of less than 0.1 FIT/Mbit.