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Nexperia B.V. 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 74LVCH16374ADGG,11

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16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state - 74LVCH16374ADGG,11 - Nexperia B.V.
Nijmegen, Netherlands
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
74LVCH16374ADGG,11
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 74LVCH16374ADGG,11
The 74LVC16374A; 74LVCH16374A is a 16-bit edge-triggered D-type flip-flop with 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 V to 3.6 V CMOS low power dissipation Multibyte flow-through standard pinout architecture Low inductance multiple supply pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold (74LVCH16374A only) High-impedance outputs when VCC = 0 V IOFF circuitry provides partial Power-down mode operation Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74LVC16374A; 74LVCH16374A is a 16-bit edge-triggered D-type flip-flop with 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Overvoltage tolerant inputs to 5.5 V
  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low power dissipation
  • Multibyte flow-through standard pinout architecture
  • Low inductance multiple supply pins for minimum noise and ground bounce
  • Direct interface with TTL levels
  • All data inputs have bus hold (74LVCH16374A only)
  • High-impedance outputs when VCC = 0 V
  • IOFF circuitry provides partial Power-down mode operation
  • Complies with JEDEC standard:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74LVCH16374ADGG,11 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74LVCH16374ADGG,11
Integrated Circuits (ICs) - Logic - Flip Flops 74LVCH16374ADGG,11
IC FF D-TYPE DUAL 8BIT 48TSSOP

IC FF D-TYPE DUAL 8BIT 48TSSOP

Supplier's Site
Flip Flops - 1727-74LVCH16374ADGG,11TR-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 2 Element D-Type 8 Bit Positive Edge 48-TFSOP (0.240", 6.10mm Width)

Flip Flop 2 Element D-Type 8 Bit Positive Edge 48-TFSOP (0.240", 6.10mm Width)

Supplier's Site Datasheet
Flip Flops - 74LVCH16374ADGG,11 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 2 Element D-Type 8 Bit Positive Edge 48-TFSOP (0.240", 6.10mm Width)

Flip Flop 2 Element D-Type 8 Bit Positive Edge 48-TFSOP (0.240", 6.10mm Width)

Supplier's Site Datasheet
Logic - Flip Flops - 74LVCH16374ADGG,11 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74LVCH16374ADGG,11
Logic - Flip Flops 74LVCH16374ADGG,11
IC FF D-TYPE DUAL 8BIT 48TSSOP

IC FF D-TYPE DUAL 8BIT 48TSSOP

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Shenzhen Shengyu Electronics Technology Limited DigiKey Quarktwin Technology Ltd. Lingto Electronic Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74LVCH16374ADGG,11 74LVCH16374ADGG,11 1727-74LVCH16374ADGG,11TR-ND 74LVCH16374ADGG,11 74LVCH16374ADGG,11
Product Name 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state Integrated Circuits (ICs) - Logic - Flip Flops Flip Flops Flip Flops Logic - Flip Flops
Flip-Flop Type D D D
Supply Voltage 1.2V; 1.5V; 1.8V; 2.5V; 3V; 3.3V; 3.6V; 1.2 - 3.6 1.65V ~ 3.6V 3.6V; 1.65V ~ 3.6V
Output Characteristics 3-State 3-State
Features ESD Protection
Propagation Delay 3.8 ns 5.4 ns
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