Nexperia B.V. Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74APW-Q100J

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Dual D-type flip-flop with set and reset; positive-edge trigger - 74LVC74APW-Q100J - Nexperia B.V.
Nijmegen, Netherlands
Dual D-type flip-flop with set and reset; positive-edge trigger
74LVC74APW-Q100J
Dual D-type flip-flop with set and reset; positive-edge trigger 74LVC74APW-Q100J
The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and from -40 °C to +125 °C 5 V tolerant inputs for interlacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints

The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • 5 V tolerant inputs for interlacing with 5 V logic
  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low power consumption
  • Direct interface with TTL levels
  • Complies with JEDEC standard:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
Supplier's Site Datasheet
Flip Flops - 1727-74LVC74APW-Q100JTR-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173", 4.40mm Width)

Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173", 4.40mm Width)

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74LVC74APW-Q100J - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74LVC74APW-Q100J
Integrated Circuits (ICs) - Logic - Flip Flops 74LVC74APW-Q100J
IC FF D-TYPE DUAL 1BIT 14TSSOP

IC FF D-TYPE DUAL 1BIT 14TSSOP

Supplier's Site
Logic - Flip Flops - 74LVC74APW-Q100J - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74LVC74APW-Q100J
Logic - Flip Flops 74LVC74APW-Q100J
IC FF D-TYPE DUAL 1BIT 14TSSOP

IC FF D-TYPE DUAL 1BIT 14TSSOP

Supplier's Site Datasheet
Flip Flops - 74LVC74APW-Q100J - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173", 4.40mm Width)

Flip Flop 2 Element D-Type 1 Bit Positive Edge 14-TSSOP (0.173", 4.40mm Width)

Supplier's Site Datasheet
 - 74LVC74APW-Q100J - Rochester Electronics
Newburyport, MA, United States
74LVC74A - Dual D-type flip-flop with set and reset; positive-edge trigger

74LVC74A - Dual D-type flip-flop with set and reset; positive-edge trigger

Supplier's Site Datasheet
Flip Flop, Aec-Q100, D, -40 To 125Deg C Rohs Compliant Nexperia - 74AH2640 - Newark, An Avnet Company
Chicago, IL, United States
Flip Flop, Aec-Q100, D, -40 To 125Deg C Rohs Compliant Nexperia
74AH2640
Flip Flop, Aec-Q100, D, -40 To 125Deg C Rohs Compliant Nexperia 74AH2640
FLIP FLOP, AEC-Q100, D, -40 TO 125DEG C ROHS COMPLIANT: YES

FLIP FLOP, AEC-Q100, D, -40 TO 125DEG C ROHS COMPLIANT: YES

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Shenzhen Shengyu Electronics Technology Limited Lingto Electronic Limited Quarktwin Technology Ltd. Rochester Electronics Newark, An Avnet Company
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74LVC74APW-Q100J 1727-74LVC74APW-Q100JTR-ND 74LVC74APW-Q100J 74LVC74APW-Q100J 74LVC74APW-Q100J 74LVC74APW-Q100J 74AH2640
Product Name Dual D-type flip-flop with set and reset; positive-edge trigger Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Logic - Flip Flops Flip Flops Flip Flop, Aec-Q100, D, -40 To 125Deg C Rohs Compliant Nexperia
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered
Supply Voltage 1.2V; 1.5V; 1.8V; 2.5V; 3V; 3.3V; 3.6V; 1.2 - 3.6 1.2V ~ 3.6V 3.6V; 1.2V ~ 3.6V
Features ESD Protection
Propagation Delay 2.5 ns 5.2 ns
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