Nexperia B.V. Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573ABQ,115

Description
The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.2 to 3.6 V Overvoltage tolerant inputs to 5.5 V CMOS low power consumption Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation High-impedance when VCC = 0 V Flow-through pinout architecture Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C
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Description
The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.2 to 3.6 V Overvoltage tolerant inputs to 5.5 V CMOS low power consumption Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation High-impedance when VCC = 0 V Flow-through pinout architecture Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C
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Suppliers

Company
Product
Description
Supplier Links
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state - 74LVC573ABQ,115 - Nexperia B.V.
Nijmegen, Netherlands
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
74LVC573ABQ,115
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 74LVC573ABQ,115
The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.2 to 3.6 V Overvoltage tolerant inputs to 5.5 V CMOS low power consumption Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation High-impedance when VCC = 0 V Flow-through pinout architecture Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.2 to 3.6 V
  • Overvoltage tolerant inputs to 5.5 V
  • CMOS low power consumption
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • High-impedance when VCC = 0 V
  • Flow-through pinout architecture
  • Complies with JEDEC standard:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Latches - 1727-7049-2-ND - DigiKey
Thief River Falls, MN, United States
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-DHVQFN (4.5x2.5)

D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-DHVQFN (4.5x2.5)

Buy Now Datasheet
Latches - 1727-7049-1-ND - DigiKey
Thief River Falls, MN, United States
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-DHVQFN (4.5x2.5)

D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-DHVQFN (4.5x2.5)

Buy Now Datasheet
Latches - 1727-7049-6-ND - DigiKey
Thief River Falls, MN, United States
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-DHVQFN (4.5x2.5)

D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-DHVQFN (4.5x2.5)

Buy Now Datasheet
Laguna Hills, CA, United States
Logic - Logic - Latches - 74LVC573ABQ,115
1009459-74LVC573ABQ,115
Logic - Logic - Latches - 74LVC573ABQ,115 1009459-74LVC573ABQ,115
Manufacturer: Nexperia USA Inc. Win Source Part Number: 1009459-74LVC573ABQ, 115 Packaging: Reel - TR Mounting: SMD (SMT) Logic Type: D-Type Transparent Latch Output Type: Tri-State Current - Output High, Low: 24mA, 24mA Independent Circuits: 1 Categories: Integrated Circuits Status: Active Temperature Range - Operating: -40°C to 125°C Case / Package: 20-DHVQFN (4.5x 2.5) Supply Voltage - Operating: 1.2 V to 3.6 V Propagation Delay Time (ns): 1.5ns Popularity: Medium Fake Threat In the Open Market: 61 pct. Supply and Demand Status: Balance

Manufacturer: Nexperia USA Inc.
Win Source Part Number: 1009459-74LVC573ABQ,115
Packaging: Reel - TR
Mounting: SMD (SMT)
Logic Type: D-Type Transparent Latch
Output Type: Tri-State
Current - Output High, Low: 24mA, 24mA
Independent Circuits: 1
Categories: Integrated Circuits
Status: Active
Temperature Range - Operating: -40°C to 125°C
Case / Package: 20-DHVQFN (4.5x 2.5)
Supply Voltage - Operating: 1.2 V to 3.6 V
Propagation Delay Time (ns): 1.5ns
Popularity: Medium
Fake Threat In the Open Market: 61 pct.
Supply and Demand Status: Balance

Buy Now Datasheet
Latches - 74LVC573ABQ,115 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-DHVQFN (4.5x2.5)

D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-DHVQFN (4.5x2.5)

Buy Now Datasheet
Integrated Circuits (ICs) - Logic - Latches - 74LVC573ABQ,115 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Latches
74LVC573ABQ,115
Integrated Circuits (ICs) - Logic - Latches 74LVC573ABQ,115
IC D-TYPE TRANSP SGL 8:8 20HVQFN

IC D-TYPE TRANSP SGL 8:8 20HVQFN

Supplier's Site
Logic - Latches - 74LVC573ABQ,115 - Lingto Electronic Limited
Shenzhen, China
Logic - Latches
74LVC573ABQ,115
Logic - Latches 74LVC573ABQ,115
IC OCTAL D TRANSP LATCH 20DHVQFN

IC OCTAL D TRANSP LATCH 20DHVQFN

Supplier's Site Datasheet
Futian, Shenzhen, China
Logic ICs >> Latches
74LVC573ABQ,115
Logic ICs >> Latches 74LVC573ABQ,115
DHVQFN-20-EP(2.5x4.5 ) Latches ROHS

DHVQFN-20-EP(2.5x4.5) Latches ROHS

Supplier's Site Datasheet
Latch, D Type Transparent, -40To125Deg C Rohs Compliant Nexperia - 74AH2634 - Newark, An Avnet Company
Chicago, IL, United States
Latch, D Type Transparent, -40To125Deg C Rohs Compliant Nexperia
74AH2634
Latch, D Type Transparent, -40To125Deg C Rohs Compliant Nexperia 74AH2634
LATCH, D TYPE TRANSPARENT, -40TO125DEG C ROHS COMPLIANT: YES

LATCH, D TYPE TRANSPARENT, -40TO125DEG C ROHS COMPLIANT: YES

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Win Source Electronics Quarktwin Technology Ltd. Shenzhen Shengyu Electronics Technology Limited Lingto Electronic Limited LCSC Electronics Technology (HK) Limited Newark, An Avnet Company
Product Category Logic Latches Logic Latches Logic Latches Logic Latches Logic Latches Logic Latches Logic Latches Logic Latches
Product Number 74LVC573ABQ,115 1727-7049-2-ND 1009459-74LVC573ABQ,115 74LVC573ABQ,115 74LVC573ABQ,115 74LVC573ABQ,115 74LVC573ABQ,115 74AH2634
Product Name Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Latches Logic - Logic - Latches - 74LVC573ABQ,115 Latches Integrated Circuits (ICs) - Logic - Latches Logic - Latches Logic ICs >> Latches Latch, D Type Transparent, -40To125Deg C Rohs Compliant Nexperia
Latch Type Transparent-D Transparent-D D; Transparent-D
Output Characteristics 3-State 3-State
Features ESD Protection
Supply Voltage +6.5 1.2V ~ 3.6V 1.2 V ~ 3.6 V 3.6V; 1.2V ~ 3.6V 3.6V
Operating Temperature 125 C (257 F) -40 to 125 C (-40 to 257 F) -40 to 125 C (-40 to 257 F) -40 to 125 C (-40 to 257 F)
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