Nexperia B.V. Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state 74LVC374APW,118

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Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state - 74LVC374APW,118 - Nexperia B.V.
Nijmegen, Netherlands
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
74LVC374APW,118
Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state 74LVC374APW,118
The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Overvoltage tolerant inputs to 5.5 V CMOS low power dissipation Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation 8-bit positive edge-triggered register Independent register and 3-state buffer operation Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.2 V to 3.6 V
  • Overvoltage tolerant inputs to 5.5 V
  • CMOS low power dissipation
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • 8-bit positive edge-triggered register
  • Independent register and 3-state buffer operation
  • Complies with JEDEC standard:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Flip Flops - 74LVC374APW,118 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)

Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74LVC374APW,118 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74LVC374APW,118
Integrated Circuits (ICs) - Logic - Flip Flops 74LVC374APW,118
IC FF D-TYPE SNGL 8BIT 20TSSOP

IC FF D-TYPE SNGL 8BIT 20TSSOP

Supplier's Site
Logic - Flip Flops - 74LVC374APW,118 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74LVC374APW,118
Logic - Flip Flops 74LVC374APW,118
IC FF D-TYPE SNGL 8BIT 20TSSOP

IC FF D-TYPE SNGL 8BIT 20TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-4034-6-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-4034-6-ND
Flip Flops 1727-4034-6-ND
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)

Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)

Supplier's Site Datasheet
Flip Flops - 1727-4034-2-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-4034-2-ND
Flip Flops 1727-4034-2-ND
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)

Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)

Supplier's Site Datasheet
Flip Flops - 1727-4034-1-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-4034-1-ND
Flip Flops 1727-4034-1-ND
Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)

Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-TSSOP (0.173", 4.40mm Width)

Supplier's Site Datasheet
D Flip Flop, Octal, 2.7Ns, Tssop-20; Logic Family / Base Number Nexperia - 33AC1283 - Newark, An Avnet Company
Chicago, IL, United States
D Flip Flop, Octal, 2.7Ns, Tssop-20; Logic Family / Base Number Nexperia
33AC1283
D Flip Flop, Octal, 2.7Ns, Tssop-20; Logic Family / Base Number Nexperia 33AC1283
D FLIP FLOP, OCTAL, 2.7NS, TSSOP-20; Logic Family / Base Number:74LVC374; Flip-Flop Type:D; Propagation Delay:2.7ns; Frequency:100MHz; Output Current:50mA; Logic Case Style:TSSOP; No. of Pins:20Pins; Trigger Type:Positive Edge; IC RoHS Compliant: Yes

D FLIP FLOP, OCTAL, 2.7NS, TSSOP-20; Logic Family / Base Number:74LVC374; Flip-Flop Type:D; Propagation Delay:2.7ns; Frequency:100MHz; Output Current:50mA; Logic Case Style:TSSOP; No. of Pins:20Pins; Trigger Type:Positive Edge; IC RoHS Compliant: Yes

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Quarktwin Technology Ltd. Shenzhen Shengyu Electronics Technology Limited Lingto Electronic Limited DigiKey Newark, An Avnet Company
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74LVC374APW,118 74LVC374APW,118 74LVC374APW,118 74LVC374APW,118 1727-4034-6-ND 33AC1283
Product Name Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Logic - Flip Flops Flip Flops D Flip Flop, Octal, 2.7Ns, Tssop-20; Logic Family / Base Number Nexperia
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered
Supply Voltage 1.2V; 1.5V; 1.8V; 2.5V; 3V; 3.3V; 3.6V; 1.2 - 3.6 3.6V; 1.65V ~ 3.6V 1.65V ~ 3.6V
Output Characteristics 3-State 3-State
Features ESD Protection
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