Nexperia B.V. Single D-type flip-flop with reset; positive-edge trigger 74LVC1G175GW-Q100H

Request a Quote Datasheet

Suppliers

Company
Product
Description
Supplier Links
Single D-type flip-flop with reset; positive-edge trigger - 74LVC1G175GW-Q100H - Nexperia B.V.
Nijmegen, Netherlands
Single D-type flip-flop with reset; positive-edge trigger
74LVC1G175GW-Q100H
Single D-type flip-flop with reset; positive-edge trigger 74LVC1G175GW-Q100H
The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 1.65 V to 5.5 V High noise immunity Overvoltage tolerant inputs to 5.5 V ±24 mA output drive (VCC = 3.0 V) CMOS low power dissipation Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)

The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range from 1.65 V to 5.5 V
  • High noise immunity
  • Overvoltage tolerant inputs to 5.5 V
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power dissipation
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance exceeds 250 mA
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8C (2.7 V to 3.6 V)
    • JESD36 (4.5 V to 5.5 V)
  • ESD protection:
    • MIL-STD-883, method 3015 exceeds 2000 V
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)
Supplier's Site Datasheet
Integrated Circuits - 74LVC1G175GW-Q100H - LIXINC Electronics Co., Limited
Hong Kong, China
Integrated Circuits
74LVC1G175GW-Q100H
Integrated Circuits 74LVC1G175GW-Q100H
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 1352462-74LVC1G175GW-Q100H - Win Source Electronics
Yishun, Singapore
Integrated Circuits (ICs) - Logic - Flip Flops
1352462-74LVC1G175GW-Q100H
Integrated Circuits (ICs) - Logic - Flip Flops 1352462-74LVC1G175GW-Q100H
Win Source Part Number: 1352462-74LVC1G175GW -Q100H Category: Integrated Circuits (ICs) - Logic - Flip Flops Temperature Range - Operating: -40°C ~ 125°C (TA) Fake Threat In the Open Market: 57 pct. Type: D-Type MSL Level: 1 (Unlimited) Mfr: Nexperia USA Inc. Series: Automotive, AEC-Q100, 74LVC Package: Tape & Reel Product Status: Active Package / Case: 6-TSSOP, SC-88, SOT-363 Supplier Device Package: 6-TSSOP Base Product Number: 74LVC1G175 Mounting Type: Surface Mount HTSUS: 8542.39.0001 REACH Status: REACH Unaffected ECCN: EAR99 Function: Reset Voltage - Supply: 1.65V ~ 5.5V Output Type: Non-Inverted Clock Frequency: 200 MHz Current - Quiescent (Iq): 10 µA Current - Output High, Low: 32mA, 32mA Max Propagation Delay @ V, Max CL: 4ns @ 5V, 50pF Number of Elements: 1 Number of Bits per Element: 1 Trigger Type: Positive Edge Input Capacitance: 2.5 pF

Win Source Part Number: 1352462-74LVC1G175GW-Q100H
Category: Integrated Circuits (ICs) - Logic - Flip Flops
Temperature Range - Operating: -40°C ~ 125°C (TA)
Fake Threat In the Open Market: 57 pct.
Type: D-Type
MSL Level: 1 (Unlimited)
Mfr: Nexperia USA Inc.
Series: Automotive, AEC-Q100, 74LVC
Package: Tape & Reel
Product Status: Active
Package / Case: 6-TSSOP, SC-88, SOT-363
Supplier Device Package: 6-TSSOP
Base Product Number: 74LVC1G175
Mounting Type: Surface Mount
HTSUS: 8542.39.0001
REACH Status: REACH Unaffected
ECCN: EAR99
Function: Reset
Voltage - Supply: 1.65V ~ 5.5V
Output Type: Non-Inverted
Clock Frequency: 200 MHz
Current - Quiescent (Iq): 10 µA
Current - Output High, Low: 32mA, 32mA
Max Propagation Delay @ V, Max CL: 4ns @ 5V, 50pF
Number of Elements: 1
Number of Bits per Element: 1
Trigger Type: Positive Edge
Input Capacitance: 2.5 pF

Supplier's Site Datasheet
Logic - Flip Flops - 74LVC1G175GW-Q100H - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74LVC1G175GW-Q100H
Logic - Flip Flops 74LVC1G175GW-Q100H
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-8421-2-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-8421-2-ND
Flip Flops 1727-8421-2-ND
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-8421-6-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-8421-6-ND
Flip Flops 1727-8421-6-ND
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-8421-1-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-8421-1-ND
Flip Flops 1727-8421-1-ND
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site Datasheet
Flip Flop, Aec-Q100, D, -40 To 125Deg C Rohs Compliant Nexperia - 74AH2520 - Newark, An Avnet Company
Chicago, IL, United States
Flip Flop, Aec-Q100, D, -40 To 125Deg C Rohs Compliant Nexperia
74AH2520
Flip Flop, Aec-Q100, D, -40 To 125Deg C Rohs Compliant Nexperia 74AH2520
FLIP FLOP, AEC-Q100, D, -40 TO 125DEG C ROHS COMPLIANT: YES

FLIP FLOP, AEC-Q100, D, -40 TO 125DEG C ROHS COMPLIANT: YES

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. LIXINC Electronics Co., Limited Win Source Electronics Lingto Electronic Limited DigiKey Newark, An Avnet Company
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74LVC1G175GW-Q100H 74LVC1G175GW-Q100H 1352462-74LVC1G175GW-Q100H 74LVC1G175GW-Q100H 1727-8421-2-ND 74AH2520
Product Name Single D-type flip-flop with reset; positive-edge trigger Integrated Circuits Integrated Circuits (ICs) - Logic - Flip Flops Logic - Flip Flops Flip Flops Flip Flop, Aec-Q100, D, -40 To 125Deg C Rohs Compliant Nexperia
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered; Positive Edge Positive-edge Triggered; Positive Edge Positive-edge Triggered
Supply Voltage 1.8V; 2.5V; 3V; 3.3V; 3.6V; 5V; 1.65 - 5.5 1.65V ~ 5.5V 1.65V ~ 5.5V 1.65V ~ 5.5V
Features ESD Protection
Propagation Delay 3.1 ns 4 ns 4 ns 4 ns
Unlock Full Specs
to access all available technical data

Similar Products

Low-power D-type flip-flop with set and reset; positive-edge trigger - 74AUP1G74GT,115 - Nexperia B.V.
Specs
Flip-Flop Type D
Triggering Positive-edge Triggered
Supply Voltage 0.8 - 3.6
View Details
6 suppliers
20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ohm termination resistors; 3-state - 74ALVT162821DGG:11 - Nexperia B.V.
Specs
Flip-Flop Type D
Supply Voltage 2.5V; 3V; 3.3V; 3.6V; 2.3 - 3.6
Features ESD Protection
View Details
2 suppliers
Dual JK flip-flop - HEF4027BT-Q100J - Nexperia B.V.
Specs
Flip-Flop Type J-K
Supply Voltage 3V; 3.3V; 3.6V; 5V; 3.0 - 15
Features ESD Protection
View Details
5 suppliers
Dual D-type flip-flop with set and reset; positive edge-trigger - 74HC74D-Q100,118 - Nexperia B.V.
Specs
Flip-Flop Type D
Triggering Positive-edge Triggered
Supply Voltage 2.5V; 3V; 3.3V; 3.6V; 5V; 2.0 - 6.0
View Details
8 suppliers