Nexperia B.V. Single D-type flip-flop with reset; positive-edge trigger 74LVC1G175GM,132

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Single D-type flip-flop with reset; positive-edge trigger - 74LVC1G175GM,132 - Nexperia B.V.
Nijmegen, Netherlands
Single D-type flip-flop with reset; positive-edge trigger
74LVC1G175GM,132
Single D-type flip-flop with reset; positive-edge trigger 74LVC1G175GM,132
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V High noise immunity Overvoltage tolerant inputs to 5.5 V ±24 mA output drive (VCC = 3.0 V) CMOS low power dissipation Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation Latch-up performance exceeds 250 mA Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V. Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C.

The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output.

The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

Features and benefits

  • Wide supply voltage range from 1.65 V to 5.5 V
  • High noise immunity
  • Overvoltage tolerant inputs to 5.5 V
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power dissipation
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • Latch-up performance exceeds 250 mA
  • Complies with JEDEC standard:
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8C (2.7 V to 3.6 V)
    • JESD36 (4.5 V to 5.5 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V.
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C.
Supplier's Site Datasheet
Flip Flops - 74LVC1G175GM,132 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Supplier's Site Datasheet
Flip Flops - 1727-74LVC1G175GM,132DKR-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE SNGL 1BIT 6XSON

IC FF D-TYPE SNGL 1BIT 6XSON

Supplier's Site Datasheet
Flip Flops - 1727-74LVC1G175GM,132TR-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE SNGL 1BIT 6XSON

IC FF D-TYPE SNGL 1BIT 6XSON

Supplier's Site Datasheet
Flip Flops - 1727-74LVC1G175GM,132CT-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE SNGL 1BIT 6XSON

IC FF D-TYPE SNGL 1BIT 6XSON

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74LVC1G175GM,132 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74LVC1G175GM,132
Integrated Circuits (ICs) - Logic - Flip Flops 74LVC1G175GM,132
IC FF D-TYPE SNGL 1BIT 6XSON

IC FF D-TYPE SNGL 1BIT 6XSON

Supplier's Site
Logic - Flip Flops - 74LVC1G175GM,132 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74LVC1G175GM,132
Logic - Flip Flops 74LVC1G175GM,132
IC FF D-TYPE SNGL 1BIT 6XSON

IC FF D-TYPE SNGL 1BIT 6XSON

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Quarktwin Technology Ltd. DigiKey Shenzhen Shengyu Electronics Technology Limited Lingto Electronic Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74LVC1G175GM,132 74LVC1G175GM,132 1727-74LVC1G175GM,132DKR-ND 74LVC1G175GM,132 74LVC1G175GM,132
Product Name Single D-type flip-flop with reset; positive-edge trigger Flip Flops Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Logic - Flip Flops
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered
Supply Voltage 1.8V; 2.5V; 3V; 3.3V; 3.6V; 5V; 1.65 - 5.5 1.65V ~ 5.5V 1.65V ~ 5.5V
Features ESD Protection
Propagation Delay 3.1 ns 4 ns
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