Nexperia B.V. 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state 74LVC16374ADGG-Q1J

The 74LVC16374A-Q100; 74LVCH16374A-Q100 is a 16-bit edge-triggered D-type flip-flop with 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops . Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Overvoltage tolerant inputs to 5.5 V
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power dissipation
• Multibyte flow-through standard pinout architecture
• Low inductance multiple supply pins for minimum noise and ground bounce
• Direct interface with TTL levels
• All data inputs have bus hold (74LVCH16374A-Q100 only)
• High-impedance outputs when V_CC = 0 V
• Complies with JEDEC standard:
• JESD8-7A (1.65 V to 1.95 V)
• JESD8-5A (2.3 V to 2.7 V)
• JESD8-C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

Flip Flop 2 Element D-Type 8 Bit Positive Edge 48-TFSOP (0.240", 6.10mm Width)

IC FF D-TYPE DUAL 8BIT 48TSSOP

"Flip Flop 2 Element D-Type 8 Bit Positive Edge 48-TFSOP (0.240"", 6.10mm Width)"

"Flip Flop 2 Element D-Type 8 Bit Positive Edge 48-TFSOP (0.240"", 6.10mm Width)"

"Flip Flop 2 Element D-Type 8 Bit Positive Edge 48-TFSOP (0.240"", 6.10mm Width)"