Nexperia B.V. Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161D,112

Description
The 74LVC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 V to 3.6 V CMOS low power dissipation Direct interface with TTL levels Asynchronous reset Synchronous counting and loading Two count enable inputs for n-bit cascading Positive edge-triggered clock Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C
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Description
The 74LVC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 V to 3.6 V CMOS low power dissipation Direct interface with TTL levels Asynchronous reset Synchronous counting and loading Two count enable inputs for n-bit cascading Positive edge-triggered clock Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C
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Suppliers

Company
Product
Description
Supplier Links
Presettable synchronous 4-bit binary counter; asynchronous reset - 74LVC161D,112 - Nexperia B.V.
Nijmegen, Netherlands
Presettable synchronous 4-bit binary counter; asynchronous reset
74LVC161D,112
Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161D,112
The 74LVC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. Features and benefits Overvoltage tolerant inputs to 5.5 V Wide supply voltage range from 1.2 V to 3.6 V CMOS low power dissipation Direct interface with TTL levels Asynchronous reset Synchronous counting and loading Two count enable inputs for n-bit cascading Positive edge-triggered clock Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74LVC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

Features and benefits

  • Overvoltage tolerant inputs to 5.5 V
  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low power dissipation
  • Direct interface with TTL levels
  • Asynchronous reset
  • Synchronous counting and loading
  • Two count enable inputs for n-bit cascading
  • Positive edge-triggered clock
  • Complies with JEDEC standard:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
 - 74LVC161D,112 - Rochester Electronics
Newburyport, MA, United States
Binary Counter, LVC/LCX/Z Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16

Binary Counter, LVC/LCX/Z Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, PDSO16

Supplier's Site Datasheet
Counters, Dividers - 1727-2013-ND - DigiKey
Thief River Falls, MN, United States
Counters, Dividers
1727-2013-ND
Counters, Dividers 1727-2013-ND
Counter IC Binary Counter 1 Element 4 Bit Positive Edge 16-SO

Counter IC Binary Counter 1 Element 4 Bit Positive Edge 16-SO

Buy Now Datasheet
Logic - Counters, Dividers - 74LVC161D,112 - Lingto Electronic Limited
Shenzhen, China
Logic - Counters, Dividers
74LVC161D,112
Logic - Counters, Dividers 74LVC161D,112
IC SYNC 4BIT BIN COUNTER 16SOIC

IC SYNC 4BIT BIN COUNTER 16SOIC

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Counters, Dividers - 74LVC161D,112 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Counters, Dividers
74LVC161D,112
Integrated Circuits (ICs) - Logic - Counters, Dividers 74LVC161D,112
IC BINARY COUNTER 4-BIT 16SO

IC BINARY COUNTER 4-BIT 16SO

Supplier's Site
Counters, Dividers - 74LVC161D,112 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Counters, Dividers
74LVC161D,112
Counters, Dividers 74LVC161D,112
Counter IC Binary Counter 1 Element 4 Bit Positive Edge 16-SO

Counter IC Binary Counter 1 Element 4 Bit Positive Edge 16-SO

Buy Now Datasheet

Technical Specifications

  Nexperia B.V. Rochester Electronics DigiKey Lingto Electronic Limited Shenzhen Shengyu Electronics Technology Limited Quarktwin Technology Ltd.
Product Category Logic Counters Logic Counters Logic Counters Logic Counters Logic Counters Logic Counters
Product Number 74LVC161D,112 74LVC161D,112 1727-2013-ND 74LVC161D,112 74LVC161D,112 74LVC161D,112
Product Name Presettable synchronous 4-bit binary counter; asynchronous reset Counters, Dividers Logic - Counters, Dividers Integrated Circuits (ICs) - Logic - Counters, Dividers Counters, Dividers
Features ESD Protection
Counter Category Synchronous; Asynchronous Synchronous Synchronous; Asynchronous Synchronous
Supply Voltage 1.2V; 1.5V; 1.8V; 2.5V; 3V; 3.3V; 3.6V; 1.2 - 3.6 1.2 V ~ 3.6 V
Package Type SO16 (SOT109-1) SO16 SOIC; "16-SOIC (0.154"", 3.90mm Width)" SOIC SOIC; 16-SOIC (0.154\", 3.90mm Width)
Logic Family TTL; CMOS; CMOS/LVTTL CMOS
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