Nexperia B.V. 8-bit serial-in/parallel-out shift register 74LV164D-Q100J

The 74LV164-Q100 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (DSA or DSB) and either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH. Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP) and enters into Q0, which is the logical AND-function of the two data inputs (DSA and DSB) that existed one set-up time prior to the rising clock edge. A LOW on the master reset input (MR) overrides all other inputs and clears the register asynchronously, forcing all outputs LOW. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide operating voltage: 1.0 V to 5.5 V Optimized for low-voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce): < 0.8 V at VCC = 3.3 V and Tamb = 25 °C Typical VOHV (output VOH undershoot): > 2 V at VCC = 3.3 V and Tamb = 25 °C Gated serial data inputs Asynchronous master reset ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints

Shift Shift Register 1 Element 8 Bit 14-SO