Nexperia B.V. Octal D-type flip-flop with reset; positive-edge trigger 74HCT273BQ,115

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Octal D-type flip-flop with reset; positive-edge trigger - 74HCT273BQ,115 - Nexperia B.V.
Nijmegen, Netherlands
Octal D-type flip-flop with reset; positive-edge trigger
74HCT273BQ,115
Octal D-type flip-flop with reset; positive-edge trigger 74HCT273BQ,115
The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC273: CMOS level For 74HCT273: TTL level Common clock and master reset Eight positive edge-triggered D-type flip-flops ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits

  • Wide supply voltage range from 2.0 V to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • Input levels:
    • For 74HC273: CMOS level
    • For 74HCT273: TTL level
  • Common clock and master reset
  • Eight positive edge-triggered D-type flip-flops
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
Flip Flops - 1727-74HCT273BQ,115TR-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE SNGL 8BIT 20DHVQFN

IC FF D-TYPE SNGL 8BIT 20DHVQFN

Supplier's Site Datasheet
 - 74HCT273BQ,115 - Rochester Electronics
Newburyport, MA, United States
74HCT273 - Octal D-type flip-flop with reset; positive-edge trigger

74HCT273 - Octal D-type flip-flop with reset; positive-edge trigger

Supplier's Site Datasheet
Logic - Flip Flops - 74HCT273BQ,115 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74HCT273BQ,115
Logic - Flip Flops 74HCT273BQ,115
IC FF D-TYPE SNGL 8BIT 20DHVQFN

IC FF D-TYPE SNGL 8BIT 20DHVQFN

Supplier's Site Datasheet
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia - 74AH2369 - Newark, An Avnet Company
Chicago, IL, United States
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia
74AH2369
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia 74AH2369
FLIP FLOP, D, -40 TO 125DEG C ROHS COMPLIANT: YES

FLIP FLOP, D, -40 TO 125DEG C ROHS COMPLIANT: YES

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. DigiKey Rochester Electronics Lingto Electronic Limited Newark, An Avnet Company
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74HCT273BQ,115 1727-74HCT273BQ,115TR-ND 74HCT273BQ,115 74HCT273BQ,115 74AH2369
Product Name Octal D-type flip-flop with reset; positive-edge trigger Flip Flops Logic - Flip Flops Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia
Flip-Flop Type D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered
Supply Voltage 5V; 4.5 - 5.5 4.5V ~ 5.5V
Features ESD Protection
Propagation Delay 15 ns 30 ns
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