Nexperia B.V. Dual JK flip-flop with set and reset; positive-edge-trigger 74HCT109PW-Q100J

Request a Quote Datasheet

Suppliers

Company
Product
Description
Supplier Links
Dual JK flip-flop with set and reset; positive-edge-trigger - 74HCT109PW-Q100J - Nexperia B.V.
Nijmegen, Netherlands
Dual JK flip-flop with set and reset; positive-edge-trigger
74HCT109PW-Q100J
Dual JK flip-flop with set and reset; positive-edge-trigger 74HCT109PW-Q100J
The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the J and K inputs together. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and from -40 °C to +125 °C J and K inputs for easy D-type flip-flop Toggle flip-flop or "do nothing" mode Wide supply voltage range: For 74HC109-Q100: from 2.0 V to 6.0 V For 74HCT109-Q100: from 4.5 V to 5.5 V CMOS low power dissipation High noise immunity Input levels: For 74HC109-Q100: CMOS level For 74HCT109-Q100: TTL level Latch-up performance exceeds 100 mA per JESD 78 Class II Level B 74HC109-Q100 complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) 74HCT109-Q100 complies with JEDEC standard JESD7A (2.0 V to 6.0 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the J and K inputs together. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • J and K inputs for easy D-type flip-flop
  • Toggle flip-flop or "do nothing" mode
  • Wide supply voltage range:
    • For 74HC109-Q100: from 2.0 V to 6.0 V
    • For 74HCT109-Q100: from 4.5 V to 5.5 V
  • CMOS low power dissipation
  • High noise immunity
  • Input levels:
    • For 74HC109-Q100: CMOS level
    • For 74HCT109-Q100: TTL level
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • 74HC109-Q100 complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • 74HCT109-Q100 complies with JEDEC standard JESD7A (2.0 V to 6.0 V)
  • ESD protection:
    • MIL-STD-883, method 3015 exceeds 2000 V
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
Supplier's Site Datasheet
Logic - Flip Flops - 74HCT109PW-Q100J - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74HCT109PW-Q100J
Logic - Flip Flops 74HCT109PW-Q100J
IC FF JK TYPE DUAL 1BIT 16TSSOP

IC FF JK TYPE DUAL 1BIT 16TSSOP

Supplier's Site Datasheet
Flip Flops - 74HCT109PW-Q100J - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

Supplier's Site Datasheet
Flip Flops - 1727-74HCT109PW-Q100JDKR-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

Supplier's Site Datasheet
Flip Flops - 1727-74HCT109PW-Q100JTR-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

Supplier's Site Datasheet
Flip Flops - 1727-74HCT109PW-Q100JCT-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

Supplier's Site Datasheet
 - 74HCT109PW-Q100J - Rochester Electronics
Newburyport, MA, United States
74HCT109 - Dual J flip-flop with set and reset

74HCT109 - Dual J flip-flop with set and reset

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74HCT109PW-Q100J - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74HCT109PW-Q100J
Integrated Circuits (ICs) - Logic - Flip Flops 74HCT109PW-Q100J
IC FF JK TYPE DUAL 1BIT 16TSSOP

IC FF JK TYPE DUAL 1BIT 16TSSOP

Supplier's Site
Dual Jk Flip Flop, -40 To 125Deg C Rohs Compliant Nexperia - 64AH9840 - Newark, An Avnet Company
Chicago, IL, United States
Dual Jk Flip Flop, -40 To 125Deg C Rohs Compliant Nexperia
64AH9840
Dual Jk Flip Flop, -40 To 125Deg C Rohs Compliant Nexperia 64AH9840
DUAL JK FLIP FLOP, -40 TO 125DEG C ROHS COMPLIANT: YES

DUAL JK FLIP FLOP, -40 TO 125DEG C ROHS COMPLIANT: YES

Supplier's Site

Technical Specifications

  Nexperia B.V. Lingto Electronic Limited Quarktwin Technology Ltd. DigiKey Rochester Electronics Shenzhen Shengyu Electronics Technology Limited Newark, An Avnet Company
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74HCT109PW-Q100J 74HCT109PW-Q100J 74HCT109PW-Q100J 1727-74HCT109PW-Q100JDKR-ND 74HCT109PW-Q100J 74HCT109PW-Q100J 64AH9840
Product Name Dual JK flip-flop with set and reset; positive-edge-trigger Logic - Flip Flops Flip Flops Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Dual Jk Flip Flop, -40 To 125Deg C Rohs Compliant Nexperia
Triggering Positive-edge Triggered Positive-edge Triggered
Supply Voltage 5V; 4.5 - 5.5 4.5V ~ 5.5V 4.5V ~ 5.5V
Features ESD Protection
Propagation Delay 17 ns 35 ns
fMAX 61 MHz 55 MHz
Unlock Full Specs
to access all available technical data

Similar Products

Dual JK flip-flop with reset; negative-edge trigger - 74HC73PW,118 - Nexperia B.V.
Specs
Flip-Flop Type J-K
Triggering Negative-edge Triggered
Supply Voltage 2.5V; 3V; 3.3V; 3.6V; 5V; 2.0 - 6.0
View Details
9 suppliers
Octal D-type flip-flop with reset; positive-edge trigger - 74AHCT273PW,118 - Nexperia B.V.
Specs
Flip-Flop Type D
Triggering Positive-edge Triggered
Supply Voltage 5V; 4.5 - 5.5
View Details
7 suppliers
Low-power D-type flip-flop; positive-edge trigger - 74AUP1G79GN,132 - Nexperia B.V.
Specs
Flip-Flop Type D
Triggering Positive-edge Triggered
Supply Voltage 0.8 - 3.6
View Details
7 suppliers
Single D-type flip-flop with reset; positive-edge trigger - 74LVC1G175GW-Q100H - Nexperia B.V.
Specs
Flip-Flop Type D
Triggering Positive-edge Triggered
Supply Voltage 1.8V; 2.5V; 3V; 3.3V; 3.6V; 5V; 1.65 - 5.5
View Details
8 suppliers