Nexperia B.V. Octal D-type transparent latch; 3-state 74HC573D,652

Description
The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Input levels: For 74HC573: CMOS level For 74HCT573: TTL level Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors and microcomputers 3-state non-inverting outputs for bus-oriented applications Common 3-state output enable input Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C
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Description
The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Input levels: For 74HC573: CMOS level For 74HCT573: TTL level Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors and microcomputers 3-state non-inverting outputs for bus-oriented applications Common 3-state output enable input Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C
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Suppliers

Company
Product
Description
Supplier Links
Octal D-type transparent latch; 3-state - 74HC573D,652 - Nexperia B.V.
Nijmegen, Netherlands
Octal D-type transparent latch; 3-state
74HC573D,652
Octal D-type transparent latch; 3-state 74HC573D,652
The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Features and benefits Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Input levels: For 74HC573: CMOS level For 74HCT573: TTL level Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors and microcomputers 3-state non-inverting outputs for bus-oriented applications Common 3-state output enable input Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C

The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Features and benefits

  • Wide supply voltage range from 2.0 V to 6.0 V
  • CMOS low power dissipation
  • High noise immunity
  • Input levels:
    • For 74HC573: CMOS level
    • For 74HCT573: TTL level
  • Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
  • Useful as input or output port for microprocessors and microcomputers
  • 3-state non-inverting outputs for bus-oriented applications
  • Common 3-state output enable input
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
  • Complies with JEDEC standards:
    • JESD8C (2.7 V to 3.6 V)
    • JESD7A (2.0 V to 6.0 V)
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Supplier's Site Datasheet
Latch ICs - 1776679 - RS Components, Ltd.
Corby, Northants, United Kingdom
Latch ICs
1776679
Latch ICs 1776679
Octal transparent D latch,74HC573D

Octal transparent D latch,74HC573D

Supplier's Site
Latches - 1727-3794-ND - DigiKey
Thief River Falls, MN, United States
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-SO

D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-SO

Buy Now Datasheet
Logic - Latches - 74HC573D,652 - Lingto Electronic Limited
Shenzhen, China
Logic - Latches
74HC573D,652
Logic - Latches 74HC573D,652
IC LATCH OCTAL D 3STATE 20SOIC

IC LATCH OCTAL D 3STATE 20SOIC

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Latches - 74HC573D,652 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Latches
74HC573D,652
Integrated Circuits (ICs) - Logic - Latches 74HC573D,652
IC D-TYPE TRANSP SGL 8:8 20SO

IC D-TYPE TRANSP SGL 8:8 20SO

Supplier's Site
Latches - 74HC573D,652 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-SO

D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-SO

Buy Now Datasheet

Technical Specifications

  Nexperia B.V. RS Components, Ltd. DigiKey Lingto Electronic Limited Shenzhen Shengyu Electronics Technology Limited Quarktwin Technology Ltd.
Product Category Logic Latches Logic Latches Logic Latches Logic Latches Logic Latches Logic Latches
Product Number 74HC573D,652 1776679 1727-3794-ND 74HC573D,652 74HC573D,652 74HC573D,652
Product Name Octal D-type transparent latch; 3-state Latch ICs Latches Logic - Latches Integrated Circuits (ICs) - Logic - Latches Latches
Latch Type Transparent-D Transparent-D; D type Transparent-D D; Transparent-D
Output Characteristics 3-State 3 state 3-State
Features ESD Protection
Supply Voltage 2.5V; 3V; 3.3V; 3.6V; 5V; 2.0 - 6.0 2V ~ 6V 2V ~ 6V
Propagation Delay 14 ns 14 ns 14 ns
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