Nexperia B.V. Low-power dual D-type flip-flop; positive-edge trigger 74AUP2G80GT,115

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Low-power dual D-type flip-flop; positive-edge trigger - 74AUP2G80GT,115 - Nexperia B.V.
Nijmegen, Netherlands
Low-power dual D-type flip-flop; positive-edge trigger
74AUP2G80GT,115
Low-power dual D-type flip-flop; positive-edge trigger 74AUP2G80GT,115
The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5 000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1 000 V Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8-B (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5 000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1 000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Yishun, Singapore
Logic - Logic - Flip Flops - 74AUP2G80GT,115
857735-74AUP2G80GT,115
Logic - Logic - Flip Flops - 74AUP2G80GT,115 857735-74AUP2G80GT,115
Manufacturer: Nexperia USA Inc. Win Source Part Number: 857735-74AUP2G80GT,1 15 Series: 74AUP Features: Flip Flop 2 Element 1 Bit Package: Reel - TR Family Name: 74AUP2G80 Categories: Integrated Circuits (ICs) ECCN: EAR99 Popularity: Medium Fake Threat In the Open Market: 82 pct. Supply and Demand Status: Limited Quantity per package: 5000 MSL Level: 1 (Unlimited) Estimated Pruduction Lead Time: 25 Weeks REACH Status: REACH Unaffected HTSUS: 8542.39.0001 Other Part Number: 568-9210-6-ND, 935280723115, 568-9210-2, 568-9210-1, 74AUP2G80GT,115-ND, 74AUP2G80GT-G, 568-9210-6, 1727-6889-1, 1727-6889-2, 74AUP2G80GT-G-ND, 1727-6889-6, 568-9210-1-ND, 74AUP2G80GT115, 568-9210-2-ND

Manufacturer: Nexperia USA Inc.
Win Source Part Number: 857735-74AUP2G80GT,115
Series: 74AUP
Features: Flip Flop 2 Element 1 Bit
Package: Reel - TR
Family Name: 74AUP2G80
Categories: Integrated Circuits (ICs)
ECCN: EAR99
Popularity: Medium
Fake Threat In the Open Market: 82 pct.
Supply and Demand Status: Limited
Quantity per package: 5000
MSL Level: 1 (Unlimited)
Estimated Pruduction Lead Time: 25 Weeks
REACH Status: REACH Unaffected
HTSUS: 8542.39.0001
Other Part Number: 568-9210-6-ND, 935280723115, 568-9210-2, 568-9210-1, 74AUP2G80GT,115-ND, 74AUP2G80GT-G, 568-9210-6, 1727-6889-1, 1727-6889-2, 74AUP2G80GT-G-ND, 1727-6889-6, 568-9210-1-ND, 74AUP2G80GT115, 568-9210-2-ND

Supplier's Site Datasheet
Integrated Circuits - 74AUP2G80GT,115 - LIXINC Electronics Co., Limited
Hong Kong, China
Integrated Circuits
74AUP2G80GT,115
Integrated Circuits 74AUP2G80GT,115
IC FF D-TYPE DUAL 1BIT 8XSON

IC FF D-TYPE DUAL 1BIT 8XSON

Supplier's Site Datasheet
 - 74AUP2G80GT,115 - Rochester Electronics
Newburyport, MA, United States
Nexperia 74AUP2G80GT - D Flip-Flop, AUP/ULP/V Series, 2-Func, Positive Edge Triggered, 1-Bit, Inverted Output, CMOS, PDSO8

Nexperia 74AUP2G80GT - D Flip-Flop, AUP/ULP/V Series, 2-Func, Positive Edge Triggered, 1-Bit, Inverted Output, CMOS, PDSO8

Supplier's Site Datasheet
Flip Flops - 1727-6889-2-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6889-2-ND
Flip Flops 1727-6889-2-ND
IC FF D-TYPE DUAL 1BIT 8XSON

IC FF D-TYPE DUAL 1BIT 8XSON

Supplier's Site Datasheet
Flip Flops - 1727-6889-6-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6889-6-ND
Flip Flops 1727-6889-6-ND
IC FF D-TYPE DUAL 1BIT 8XSON

IC FF D-TYPE DUAL 1BIT 8XSON

Supplier's Site Datasheet
Flip Flops - 1727-6889-1-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6889-1-ND
Flip Flops 1727-6889-1-ND
IC FF D-TYPE DUAL 1BIT 8XSON

IC FF D-TYPE DUAL 1BIT 8XSON

Supplier's Site Datasheet
Logic - Flip Flops - 74AUP2G80GT,115 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74AUP2G80GT,115
Logic - Flip Flops 74AUP2G80GT,115
IC FF D-TYPE DUAL 1BIT 8XSON

IC FF D-TYPE DUAL 1BIT 8XSON

Supplier's Site Datasheet
Logic - Flip Flops -  - Nova Technology(HK) Co.,Ltd
Futian District, Shenzhen, China
Logic - Flip Flops
Logic - Flip Flops
Flip Flop Element Bit

Flip Flop Element Bit

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Win Source Electronics LIXINC Electronics Co., Limited Rochester Electronics DigiKey Lingto Electronic Limited Nova Technology(HK) Co.,Ltd
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74AUP2G80GT,115 857735-74AUP2G80GT,115 74AUP2G80GT,115 74AUP2G80GT,115 1727-6889-2-ND 74AUP2G80GT,115
Product Name Low-power dual D-type flip-flop; positive-edge trigger Logic - Logic - Flip Flops - 74AUP2G80GT,115 Integrated Circuits Flip Flops Logic - Flip Flops Logic - Flip Flops
Flip-Flop Type D D D D
Triggering Positive-edge Triggered Positive-edge Triggered; Positive Edge Positive-edge Triggered Positive-edge Triggered
Supply Voltage 0.8 - 3.6 0.8V ~ 3.6V 0.8V ~ 3.6V
Features ESD Protection
Propagation Delay 9.1 ns 6.4 ns 6.4 ns
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