Nexperia B.V. Low-power D-type flip-flop with set and reset; positive-edge trigger 74AUP1G74GN,115

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Low-power D-type flip-flop with set and reset; positive-edge trigger - 74AUP1G74GN,115 - Nexperia B.V.
Nijmegen, Netherlands
Low-power D-type flip-flop with set and reset; positive-edge trigger
74AUP1G74GN,115
Low-power D-type flip-flop with set and reset; positive-edge trigger 74AUP1G74GN,115
The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V CMOS low power dissipation High noise immunity Overvoltage tolerant inputs to 3.6 V Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8C (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5 kV MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1 kV Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V
  • CMOS low power dissipation
  • High noise immunity
  • Overvoltage tolerant inputs to 3.6 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8C (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5 kV
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1 kV
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Flip Flops - 74AUP1G74GN,115 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-XFDFN

Supplier's Site Datasheet
 - 74AUP1G74GN,115 - Rochester Electronics
Newburyport, MA, United States
Nexperia 74AUP1G74GN - D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO8

Nexperia 74AUP1G74GN - D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO8

Supplier's Site Datasheet
Logic - Flip Flops - 74AUP1G74GN,115 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74AUP1G74GN,115
Logic - Flip Flops 74AUP1G74GN,115
IC FF D-TYPE SNGL 1BIT 8XSON

IC FF D-TYPE SNGL 1BIT 8XSON

Supplier's Site Datasheet
Flip Flops - 1727-6839-2-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6839-2-ND
Flip Flops 1727-6839-2-ND
Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-XFDFN

Supplier's Site Datasheet
Flip Flops - 1727-6839-1-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6839-1-ND
Flip Flops 1727-6839-1-ND
Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-XFDFN

Supplier's Site Datasheet
Flip Flops - 1727-6839-6-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6839-6-ND
Flip Flops 1727-6839-6-ND
Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 8-XFDFN

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74AUP1G74GN,115 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74AUP1G74GN,115
Integrated Circuits (ICs) - Logic - Flip Flops 74AUP1G74GN,115
IC FF D-TYPE SNGL 1BIT 8XSON

IC FF D-TYPE SNGL 1BIT 8XSON

Supplier's Site
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia - 74AH2266 - Newark, An Avnet Company
Chicago, IL, United States
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia
74AH2266
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia 74AH2266
FLIP FLOP, D, -40 TO 125DEG C ROHS COMPLIANT: YES

FLIP FLOP, D, -40 TO 125DEG C ROHS COMPLIANT: YES

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Quarktwin Technology Ltd. Rochester Electronics Lingto Electronic Limited DigiKey Shenzhen Shengyu Electronics Technology Limited Newark, An Avnet Company
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74AUP1G74GN,115 74AUP1G74GN,115 74AUP1G74GN,115 74AUP1G74GN,115 1727-6839-2-ND 74AUP1G74GN,115 74AH2266
Product Name Low-power D-type flip-flop with set and reset; positive-edge trigger Flip Flops Logic - Flip Flops Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia
Flip-Flop Type D D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered
Supply Voltage 0.8 - 3.6 3.6V; 0.8V ~ 3.6V 0.8V ~ 3.6V
Features ESD Protection
Propagation Delay 9.2 ns 5.8 ns
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