Nexperia B.V. Low-power D-type flip-flop; positive-edge trigger; 3-state 74AUP1G374GW,125

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Low-power D-type flip-flop; positive-edge trigger; 3-state - 74AUP1G374GW,125 - Nexperia B.V.
Nijmegen, Netherlands
Low-power D-type flip-flop; positive-edge trigger; 3-state
74AUP1G374GW,125
Low-power D-type flip-flop; positive-edge trigger; 3-state 74AUP1G374GW,125
The 74AUP1G374 is a single D-type flip-flop; positive-edge trigger (3-state). Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity CMOS low power dissipation Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A. Exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74AUP1G374 is a single D-type flip-flop; positive-edge trigger (3-state). Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • CMOS low power dissipation
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.65 V to 1.95 V)
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8C (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A. Exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Overvoltage tolerant inputs to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74AUP1G374GW,125 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74AUP1G374GW,125
Integrated Circuits (ICs) - Logic - Flip Flops 74AUP1G374GW,125
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site
Flip Flops - 74AUP1G374GW,125 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363

Supplier's Site Datasheet
 - 74AUP1G374GW,125 - Rochester Electronics
Newburyport, MA, United States
Nexperia 74AUP1G374GW - D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO6

Nexperia 74AUP1G374GW - D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO6

Supplier's Site Datasheet
Flip Flops - 1727-6833-6-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6833-6-ND
Flip Flops 1727-6833-6-ND
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363

Supplier's Site Datasheet
Flip Flops - 1727-6833-1-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6833-1-ND
Flip Flops 1727-6833-1-ND
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363

Supplier's Site Datasheet
Flip Flops - 1727-6833-2-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6833-2-ND
Flip Flops 1727-6833-2-ND
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363

Supplier's Site Datasheet
Logic - Flip Flops - 74AUP1G374GW,125 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74AUP1G374GW,125
Logic - Flip Flops 74AUP1G374GW,125
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Shenzhen Shengyu Electronics Technology Limited Quarktwin Technology Ltd. Rochester Electronics DigiKey Lingto Electronic Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74AUP1G374GW,125 74AUP1G374GW,125 74AUP1G374GW,125 74AUP1G374GW,125 1727-6833-6-ND 74AUP1G374GW,125
Product Name Low-power D-type flip-flop; positive-edge trigger; 3-state Integrated Circuits (ICs) - Logic - Flip Flops Flip Flops Flip Flops Logic - Flip Flops
Flip-Flop Type D D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered
Supply Voltage 0.8 - 3.6 3.6V; 0.8V ~ 3.6V 0.8V ~ 3.6V
Output Characteristics 3-State 3-State
Features ESD Protection
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