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Nexperia B.V. Low-power D-type flip-flop with reset; positive-edge trigger 74AUP1G175GW-Q100H

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Low-power D-type flip-flop with reset; positive-edge trigger - 74AUP1G175GW-Q100H - Nexperia B.V.
Nijmegen, Netherlands
Low-power D-type flip-flop with reset; positive-edge trigger
74AUP1G175GW-Q100H
Low-power D-type flip-flop with reset; positive-edge trigger 74AUP1G175GW-Q100H
The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flop and output to be reset to LOW. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 0.8 V to 3.6 V CMOS low power dissipation High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8C (2.7 V to 3.6 V) Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flop and output to be reset to LOW. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)
    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C
  • Wide supply voltage range from 0.8 V to 3.6 V
  • CMOS low power dissipation
  • High noise immunity
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8C (2.7 V to 3.6 V)
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Overvoltage tolerant inputs to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Supplier's Site Datasheet
Flip Flops - 1727-74AUP1G175GW-Q100HCT-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-74AUP1G175GW-Q100HDKR-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-74AUP1G175GW-Q100HTR-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363

Supplier's Site Datasheet
Flip Flops - 74AUP1G175GW-Q100H - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363

Supplier's Site Datasheet
Logic - Flip Flops - 74AUP1G175GW-Q100H - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74AUP1G175GW-Q100H
Logic - Flip Flops 74AUP1G175GW-Q100H
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74AUP1G175GW-Q100H - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74AUP1G175GW-Q100H
Integrated Circuits (ICs) - Logic - Flip Flops 74AUP1G175GW-Q100H
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site

Technical Specifications

  Nexperia B.V. DigiKey Quarktwin Technology Ltd. Lingto Electronic Limited Shenzhen Shengyu Electronics Technology Limited
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74AUP1G175GW-Q100H 1727-74AUP1G175GW-Q100HCT-ND 74AUP1G175GW-Q100H 74AUP1G175GW-Q100H 74AUP1G175GW-Q100H
Product Name Low-power D-type flip-flop with reset; positive-edge trigger Flip Flops Flip Flops Logic - Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered
Supply Voltage 0.8 - 3.6 0.8V ~ 3.6V 3.6V; 0.8V ~ 3.6V
Features ESD Protection
Propagation Delay 7.4 ns 5.7 ns
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