Nexperia B.V. Low-power D-type flip-flop with reset; positive-edge trigger 74AUP1G175GW,125

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Low-power D-type flip-flop with reset; positive-edge trigger - 74AUP1G175GW,125 - Nexperia B.V.
Nijmegen, Netherlands
Low-power D-type flip-flop with reset; positive-edge trigger
74AUP1G175GW,125
Low-power D-type flip-flop with reset; positive-edge trigger 74AUP1G175GW,125
The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flop and output to be reset to LOW. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity CMOS low power dissipation Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8C (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flop and output to be reset to LOW. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • CMOS low power dissipation
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8C (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Overvoltage tolerant inputs to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74AUP1G175GW,125 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74AUP1G175GW,125
Integrated Circuits (ICs) - Logic - Flip Flops 74AUP1G175GW,125
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site
Flip Flops - 1727-6027-6-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6027-6-ND
Flip Flops 1727-6027-6-ND
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-6027-1-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6027-1-ND
Flip Flops 1727-6027-1-ND
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site Datasheet
Flip Flops - 1727-6027-2-ND - DigiKey
Thief River Falls, MN, United States
Flip Flops
1727-6027-2-ND
Flip Flops 1727-6027-2-ND
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site Datasheet
Flip Flops - 74AUP1G175GW,125 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-TSSOP, SC-88, SOT-363

Supplier's Site Datasheet
Logic - Flip Flops - 74AUP1G175GW,125 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74AUP1G175GW,125
Logic - Flip Flops 74AUP1G175GW,125
IC FF D-TYPE SNGL 1BIT 6TSSOP

IC FF D-TYPE SNGL 1BIT 6TSSOP

Supplier's Site Datasheet
Yishun, Singapore
Logic - Logic - Flip Flops - 74AUP1G175GW,125
1007770-74AUP1G175GW,125
Logic - Logic - Flip Flops - 74AUP1G175GW,125 1007770-74AUP1G175GW,125
Manufacturer: Nexperia USA Inc. Win Source Part Number: 1007770-74AUP1G175GW ,125 Packaging: Reel - TR Type: D-Type Mounting: SMD (SMT) Output Type: Non-Inverted Current - Output High, Low: 4mA, 4mA Number of Elements: 1 Number of Bits per Element: 1 Max Propagation Delay @ V, Max CL: 5.7ns @ 3.3V, 30pF Trigger Type: Positive Edge Current - Quiescent: 500nA Input Capacitance: 0.8pF Categories: Integrated Circuits Status: Active Temperature Range - Operating: -40°C to 125°C (TA) Dimension: 6-TSSOP, SC-88, SOT-363 Purpose: Reset Supply Voltage - Operating: 0.8 V to 3.6 V Max Frequency: 300MHz Popularity: Medium Fake Threat In the Open Market: 47 pct. Supply and Demand Status: Balance

Manufacturer: Nexperia USA Inc.
Win Source Part Number: 1007770-74AUP1G175GW,125
Packaging: Reel - TR
Type: D-Type
Mounting: SMD (SMT)
Output Type: Non-Inverted
Current - Output High, Low: 4mA, 4mA
Number of Elements: 1
Number of Bits per Element: 1
Max Propagation Delay @ V, Max CL: 5.7ns @ 3.3V, 30pF
Trigger Type: Positive Edge
Current - Quiescent: 500nA
Input Capacitance: 0.8pF
Categories: Integrated Circuits
Status: Active
Temperature Range - Operating: -40°C to 125°C (TA)
Dimension: 6-TSSOP, SC-88, SOT-363
Purpose: Reset
Supply Voltage - Operating: 0.8 V to 3.6 V
Max Frequency: 300MHz
Popularity: Medium
Fake Threat In the Open Market: 47 pct.
Supply and Demand Status: Balance

Supplier's Site Datasheet
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia - 74AH2254 - Newark, An Avnet Company
Chicago, IL, United States
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia
74AH2254
Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia 74AH2254
FLIP FLOP, D, -40 TO 125DEG C ROHS COMPLIANT: YES

FLIP FLOP, D, -40 TO 125DEG C ROHS COMPLIANT: YES

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Shenzhen Shengyu Electronics Technology Limited DigiKey Quarktwin Technology Ltd. Lingto Electronic Limited Win Source Electronics Newark, An Avnet Company
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74AUP1G175GW,125 74AUP1G175GW,125 1727-6027-6-ND 74AUP1G175GW,125 74AUP1G175GW,125 1007770-74AUP1G175GW,125 74AH2254
Product Name Low-power D-type flip-flop with reset; positive-edge trigger Integrated Circuits (ICs) - Logic - Flip Flops Flip Flops Flip Flops Logic - Flip Flops Logic - Logic - Flip Flops - 74AUP1G175GW,125 Flip Flop, D, -40 To 125Deg C Rohs Compliant Nexperia
Flip-Flop Type D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered; Positive Edge
Supply Voltage 0.8 - 3.6 0.8V ~ 3.6V 3.6V; 0.8V ~ 3.6V 0.8 V ~ 3.6 V
Features ESD Protection
Propagation Delay 7.4 ns 5.7 ns 5.7 ns
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