Nexperia B.V. Low-power D-type flip-flop with reset; positive-edge trigger 74AUP1G175GN,132

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Low-power D-type flip-flop with reset; positive-edge trigger - 74AUP1G175GN,132 - Nexperia B.V.
Nijmegen, Netherlands
Low-power D-type flip-flop with reset; positive-edge trigger
74AUP1G175GN,132
Low-power D-type flip-flop with reset; positive-edge trigger 74AUP1G175GN,132
The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flop and output to be reset to LOW. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity CMOS low power dissipation Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8C (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption; ICC = 0.9 μA (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flop and output to be reset to LOW. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • CMOS low power dissipation
  • Complies with JEDEC standards:
    • JESD8-12 (0.8 V to 1.3 V)
    • JESD8-11 (0.9 V to 1.65 V)
    • JESD8-7 (1.2 V to 1.95 V)
    • JESD8-5 (1.8 V to 2.7 V)
    • JESD8C (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F Class 3A exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Overvoltage tolerant inputs to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial Power-down mode operation
  • Multiple package options
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C
Supplier's Site Datasheet
Logic - Flip Flops - 74AUP1G175GN,132 - Lingto Electronic Limited
Shenzhen, China
Logic - Flip Flops
74AUP1G175GN,132
Logic - Flip Flops 74AUP1G175GN,132
IC FF D-TYPE SNGL 1BIT 6XSON

IC FF D-TYPE SNGL 1BIT 6XSON

Supplier's Site Datasheet
Flip Flops - 74AUP1G175GN,132 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Supplier's Site Datasheet
Flip Flops - 74AUP1G175GN,132 - Quarktwin Technology Ltd.
Shenzhen, Guangdong, China
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Supplier's Site Datasheet
Integrated Circuits (ICs) - Logic - Flip Flops - 74AUP1G175GN,132 - Shenzhen Shengyu Electronics Technology Limited
Futian, China
Integrated Circuits (ICs) - Logic - Flip Flops
74AUP1G175GN,132
Integrated Circuits (ICs) - Logic - Flip Flops 74AUP1G175GN,132
IC FF D-TYPE SNGL 1BIT 6XSON

IC FF D-TYPE SNGL 1BIT 6XSON

Supplier's Site
 - 74AUP1G175GN,132 - Rochester Electronics
Newburyport, MA, United States
Nexperia 74AUP1G175GN - D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output

Nexperia 74AUP1G175GN - D Flip-Flop, AUP/ULP/V Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output

Supplier's Site Datasheet
Flip Flops - 1727-74AUP1G175GN,132DKR-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE SNGL 1BIT 6XSON

IC FF D-TYPE SNGL 1BIT 6XSON

Supplier's Site Datasheet
Flip Flops - 1727-74AUP1G175GN,132CT-ND - DigiKey
Thief River Falls, MN, United States
IC FF D-TYPE SNGL 1BIT 6XSON

IC FF D-TYPE SNGL 1BIT 6XSON

Supplier's Site Datasheet
Flip Flops - 1727-74AUP1G175GN,132TR-ND - DigiKey
Thief River Falls, MN, United States
Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Flip Flop 1 Element D-Type 1 Bit Positive Edge 6-XFDFN

Supplier's Site Datasheet
Logic - Flip Flops - 74AUP1G175GN,132 - Nova Technology(HK) Co.,Ltd
Futian District, Shenzhen, China
Logic - Flip Flops
74AUP1G175GN,132
Logic - Flip Flops 74AUP1G175GN,132
Flip Flop Element Bit

Flip Flop Element Bit

Supplier's Site Datasheet

Technical Specifications

  Nexperia B.V. Lingto Electronic Limited Quarktwin Technology Ltd. Shenzhen Shengyu Electronics Technology Limited Rochester Electronics DigiKey Nova Technology(HK) Co.,Ltd
Product Category Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops Flip-Flops
Product Number 74AUP1G175GN,132 74AUP1G175GN,132 74AUP1G175GN,132 74AUP1G175GN,132 74AUP1G175GN,132 1727-74AUP1G175GN,132DKR-ND 74AUP1G175GN,132
Product Name Low-power D-type flip-flop with reset; positive-edge trigger Logic - Flip Flops Flip Flops Integrated Circuits (ICs) - Logic - Flip Flops Flip Flops Logic - Flip Flops
Flip-Flop Type D D D D
Triggering Positive-edge Triggered Positive-edge Triggered Positive-edge Triggered
Supply Voltage 0.8 - 3.6 3.6V; 0.8V ~ 3.6V 0.8V ~ 3.6V
Features ESD Protection
Propagation Delay 7.4 ns 5.7 ns
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